Vertical transistors
A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.
1. A vertical transistor comprising:
a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region, the top source/drain region and the channel region having a top interface, the bottom source/drain region and the channel region having a bottom interface;
the channel region being crystalline and having an average crystal grain size of its crystal grains that is less than 20 nanometers; and
the channel region at the top interface or at the bottom interface having greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces.
2. The vertical transistor of claim 1 wherein the average crystal grain size of the channel region is no greater than 15 nanometers.
3. The vertical transistor of claim 2 wherein the average crystal grain size of the channel region is no greater than 10 nanometers.
4. The vertical transistor of claim 1 wherein the average crystal grain size of the channel region is no less than 5 nanometers.
5. The vertical transistor of claim 1 wherein the average crystal grain size of the channel region is from 5 nanometers to 15 nanometers.
6. The vertical transistor of claim 1 wherein the top and bottom source/drain regions are crystalline.
7. The vertical transistor of claim 1 wherein all of the crystal grains in the channel region at the top interface or at the bottom interface have horizontal texture.
8. The vertical transistor of claim 1 wherein less-than-all of the crystal grains in the channel region at the top interface or at the bottom interface have horizontal texture.
9. The vertical transistor of claim 1 wherein the channel region at the top interface has the greater horizontal texture.
10. The vertical transistor of claim 1 wherein the channel region at the bottom interface has the greater horizontal texture.
11. The vertical transistor of claim 1 wherein the channel region at only one of the top and bottom interfaces has the greater horizontal texture.
12. The vertical transistor of claim 11 wherein the channel region at the top interface has the greater horizontal texture.
13. The vertical transistor of claim 11 wherein the channel region at the bottom interface has the greater horizontal texture.
14. The vertical transistor of claim 1 wherein the channel region at both of the top and bottom interfaces has the greater horizontal texture.
15. The vertical transistor of claim 1 wherein some of the crystal grains in the volume of the channel region that is vertically between the crystal grains that are at the top and bottom interfaces have horizontal texture.
16. The vertical transistor of claim 1 wherein none of the crystal grains in the volume of the channel region that is vertically between the crystal grains that are at the top and bottom interfaces have horizontal texture.
17. The vertical transistor of claim 1 wherein the greater horizontal texture is exactly horizontal and the vertical transistor is exactly vertical.
18. A vertical transistor comprising:
a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region, the top source/drain region and the channel region having a top interface, the bottom source/drain region and the channel region having a bottom interface;
the channel region being crystalline and having an average crystal grain size of its crystal grains from 5 nanometers to 10 nanometers; and
the channel region at the top interface having greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces.
19. The vertical transistor of claim 18 wherein all of the crystal grains in the channel region at the top interface have horizontal texture.
20. The vertical transistor of claim 18 wherein less-than-all of the crystal grains in the channel region at the top interface have horizontal texture.
21. The vertical transistor of claim 18 wherein the greater horizontal texture is exactly horizontal and the vertical transistor is exactly vertical.
22. A vertical transistor comprising:
a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region, the top source/drain region and the channel region having a top interface, the bottom source/drain region and the channel region having a bottom interface;
the channel region being crystalline and having an average crystal grain size of its crystal grains from 5 nanometers to 10 nanometers; and
the channel region at the bottom interface having greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces.
23. The vertical transistor of claim 22 wherein all of the crystal grains in the channel region at the bottom interface have horizontal texture.
24. The vertical transistor of claim 22 wherein less-than-all of the crystal grains in the channel region at the bottom interface have horizontal texture.
25. The vertical transistor of claim 22 wherein the greater horizontal texture is exactly horizontal and the vertical transistor is exactly vertical.
26. A vertical transistor comprising:
a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region, the top source/drain region and the channel region having a top interface, the bottom source/drain region and the channel region having a bottom interface;
the channel region being crystalline and having an average crystal grain size of its crystal grains that is from 5 nanometers to 10 nanometers; and
at least some of the crystal grains in the channel region at the top interface, at least some of the crystal grains in the channel region at the bottom interface, and at least some of the crystal grains of the channel region that are vertically between the crystal grains that are at the top and bottom interfaces having horizontal texture; the channel region at the top and bottom interfaces having greater horizontal texture than volume of the crystal grains that are vertically between the crystal grains that are at the top and bottom interfaces.
27. The vertical transistor of claim 26 wherein amount of horizontal texture in the channel region at the top interface and amount of horizontal texture in the channel region at the bottom interface are the same relative one another.
28. The vertical transistor of claim 26 wherein the greater horizontal texture is exactly horizontal and the vertical transistor is exactly vertical.