IP Library Granted Patent US 11,637,657
Granted Patent B2
US 11,637,657 · App. 16/428,841 · Granted Apr 25, 2023

Low-latency forward error correction for high-speed serial links

Inventor: Debendra Das Sharma (Saratoga, CA)
Assignee: Intel Corporation
H04L1/0063H04L1/1692
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Quick Facts
Patent No.
US 11,637,657
App. No.
16/428,841
Granted
Apr 25, 2023
Kind
B2
Abstract

Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link.

Claims (37)

1. An apparatus comprising:

a port for transmitting data; and

a link coupled to the port to:

determine a size of a burst of data to be transmitted across the link;

determine a plurality of error correcting codes for forward error correction of the burst of data based on the size of the burst of data; and

transmit the burst of data and the plurality of error correcting codes across the link, wherein the error correcting code words are interleaved in the transmission such that three consecutive bytes in the transmission include a first byte comprising a portion of a first error correcting code, a second byte comprising a portion of a second error correcting code, and a third byte comprising a portion of a third error correcting code.

2. The apparatus of claim 1 , wherein the port is to:

determine a plurality of error correcting codes based on the size of the burst of data by determining a number of consecutive symbols the burst of data will utilize; and identify a number of error correcting codes for each of the consecutive symbols of the burst of data.

3. The apparatus of claim 1 , wherein the port is to:

divide a burst of data into a subset of symbols;

determine a number of consecutive symbols forming the subset of symbols that spans the entire number of bits forming the burst of data; and

determine a number of error correcting codes based on the number of consecutive symbols.

4. The apparatus of claim 3 , wherein an error correcting code from the plurality of error correcting codes corresponds to one symbol from the number of consecutive symbols.

5. The apparatus of claim 1 , wherein the port is to:

determine a bandwidth utilization for the link;

determine a length of error correcting code for forward error correction using the bandwidth utilization;

encode a physical layer token with the length of error correcting code; and

transmit the physical layer token across each lane of the link.

6. The apparatus of claim 5 , wherein the physical layer token is transmitted as a last double word of a previous forward error correction block.

7. A method comprising:

determining a size of a burst of data to be transmitted across a link;

determining a plurality of error correcting codes for forward error correction of the burst of data based on the size of the burst of data; and

transmitting the burst of data and the error correcting code across the link, wherein the error correcting code words are interleaved in the transmission such that three consecutive bytes in the transmission include a first byte comprising a portion of a first error correcting code, a second byte comprising a portion of a second error correcting code, and a third byte comprising a portion of a third error correcting code.

8. The method of claim 7 , further comprising:

determining a plurality of error correcting codes based on the size of the burst of data by determining a number of consecutive symbols the burst of data will utilize; and

identifying a number of error correcting codes for each of the consecutive symbols of the burst of data.

9. The method of claim 7 , further comprising:

dividing a burst of data into a subset of symbols;

determining a number of consecutive symbols forming the subset of symbols that spans the entire number of bits forming the burst of data; and

determine a number of error correcting codes based on the number of consecutive symbols.

10. The method of claim 9 , wherein an error correcting code from the plurality of error correcting codes corresponds to one symbol from the number of consecutive symbols.

11. The method of claim 7 , further comprising:

determining a bandwidth utilization for the link;

determining a length of error correcting code for forward error correction using the bandwidth utilization;

encoding a physical layer token with the length of error correcting code; and

transmitting the physical layer token across each lane of the link.

12. The method of claim 11 , wherein the physical layer token is transmitted as a last double word of a previous forward error correction block.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ATTORNEY DOCKET NUMBER ON THE ASSIGNMENT DOCUMENT IS AB9145-US PREVIOUSLY RECORDED AT REEL: 051489 FRAME: 0677. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 3, 2022
From: DAS SHARMA, DEBENDRA
To: INTEL CORPORATION
Reel/Frame 059318/0358 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: DAS SHARMA, DEBENDRA
To: INTEL CORPORATION
Reel/Frame 051489/0677 →
Continuity (2)
Provisional Application 62806194 · Feb 15, 2019
Related Publication 20190305888A1 · Oct 3, 2019