Method and device for balancing a supply current from multiple power supply units based on a common load share signal
A method, device, and system for balancing a supply current in a Power Supply Units (PSUs). The system includes a plurality of PSUs connected in parallel to a power bus. The method includes detecting a falling edge in a common Load Share (LS) signal and, in response to detecting the falling edge of the LS signal, enabling a field effect transistor (FET) and starting a timer. Prior to starting the timer, a time trigger is determined for the timer based on a current output level of a power source in the PSU. The method includes outputting a current at the current output level for the duration of the time trigger and, at the time trigger, releasing the FET and resetting the timer. The PSU includes a processor that monitors the LS signal. The LS signal determines a timing for outputting current by the PSU.
1. A method of balancing a supply current in a Power Supply Unit (PSU), the method comprising:
detecting a falling edge interrupt associated with a common Load Share (LS) signal;
in response to detecting the falling edge of the LS signal, enabling a field effect transistor (FET) and starting a timer;
prior to starting the timer, determining a time trigger for the timer based on a current output level of a power source in the PSU, wherein:
the time trigger for the timer is determined based on the current output level and a fixed rate in milli-seconds per ampere, and
the time trigger is further limited to a minimum and maximum value of time;
outputting a current at the current output level for the duration of the time trigger; and
at the time trigger, releasing the FET and resetting the timer.
2. The method of claim 1 , wherein enabling the FET causes the LS signal associated with the PSU and a second PSU to transition from a HIGH state to a LOW state.
3. The method of claim 1 , wherein releasing the FET causes the LS signal to transition from a LOW state to a HIGH state.
4. The method of claim 1 , the time trigger for the timer is determined based on a ratio of the output current level of the PSU to a maximum current level.
5. A Power Supply Unit (PSU) comprising:
a power source that supplies an output current of the PSU;
a current sensing device that measures the current output from the power source;
a processor that monitors a Load Share (LS) signal, wherein the LS signal determines a timing for outputting current by the PSU and the processor is adapted to:
detect a falling edge interrupt associated with the LS signal;
in response to detecting the falling edge of the LS signal, enable the FET and start a timer;
prior to starting the timer, determine a time trigger for the timer based on a current output level of a power source in the PSU, wherein:
the time trigger for the timer is determined based on the current output level and a fixed rate in milli-seconds per ampere, and
the time trigger is further limited to a minimum and maximum value of time;
output a current at the current output level for a duration of the time trigger; and
after the duration, release the FET and reset the timer; and
circuitry for controlling the timing of the output current and the LS signal.
6. The PSU of claim 5 , the circuitry comprising: a Field Effect Transistor (FET), a resistor, and a diode and an input voltage.
7. The PSU of claim 6 , wherein the FET, the resistor, the diode, and the input voltage are connected in series.
8. The PSU of claim 5 , wherein enabling the FET causes the LS signal associated with the PSU and a second PSU to transition from a HIGH state to a LOW state.
9. The PSU of claim 5 , wherein releasing the FET causes the LS signal to transition from a LOW state to a HIGH state.
10. The PSU of claim 5 , wherein the time trigger for the timer is determined based on a ratio of the output current level of the PSU to a maximum current level.
11. A system for providing power, the system comprising:
a plurality of Power Storage Units (PSUs) connected in parallel to a power bus,
wherein each PSU comprises:
a power source that supplies an output current of the PSU;
a current sensing device that measures the current output from the power source;
a processor that monitors a Load Share (LS) signal, wherein the LS signal determines a timing for outputting current by the PSU and the processor is adapted to:
detect a falling edge interrupt associated with the LS signal;
in response to detecting the falling edge of the LS signal, enable the FET and start a timer;
prior to starting the timer, determine a time trigger for the timer based on a current output level of a power source in the PSU, wherein:
the time trigger for the timer is determined based on the current output level and a fixed rate in milli-seconds per ampere, and
the time trigger is further limited to a minimum and maximum value of time;
output a current at the current output level for a duration of the time trigger; and
after the duration, release the FET and reset the timer; and
circuitry for controlling the timing of the output current based on the LS signal.
12. The system of claim 11 , wherein enabling the FET in a first PSU of the plurality of PSUs causes the LS signal associated with the first PSU and a second PSU to transition from a HIGH state to a LOW state.
13. The system of claim 11 , wherein releasing the FET in a second PSU of the plurality of PSUs causes the LS signal to transition from a LOW state to a HIGH state.
14. The system of claim 11 , wherein:
enabling the FET in a first PSU of the plurality of PSUs causes the LS signal to transition from a HIGH state to a LOW state, wherein the output voltage level of the first PSU is a lowest output voltage of the plurality of PSUs; and
releasing the FET in a second PSU of the plurality of PSUs causes the LS signal to transition from a LOW state to a HIGH state, wherein the output voltage level of the second PSU is a highest output voltage of the plurality of PSUs.