Prefetch disable of memory requests targeting data lacking locality
A system and method for efficiently processing memory requests are described. A processing unit includes at least a processor core, a cache, and a non-cache storage buffer capable of storing data prevented from being stored in the cache. While processing a memory request targeting the non-cache storage buffer, the processor core inspects a flag stored in a tag of the memory request. The processor core prevents data prefetching into one or more of the non-cache storage buffer and the cache based on determining the flag specifies preventing data prefetching into one or more of the non-cache storage buffer and the cache using the target address of the memory request during processing of this instance of the memory request. While processing a prefetch hint instruction, the processor core determines from the tag whether to prevent prefetching.
1. An apparatus comprising:
a non-cache storage buffer; and
circuitry configured to:
receive a first memory request targeting the non-cache storage buffer;
prevent data prefetching into the non-cache storage buffer based at least in part on the first memory request;
receive a second memory request targeting the non-cache storage buffer;
determine that the second memory request comprises an indication specifying that data prefetching is allowed using a target address of the first memory request; and
allow data prefetching into the non-cache storage buffer based at least in part on the second memory request.
2. The apparatus as recited in claim 1 , wherein the circuitry is further configured to prevent data prefetching into the non-cache storage buffer based at least in part on the first memory request, responsive to the first memory request comprising a first indication specifying that data prefetching is prevented using a target address of the first memory request.
3. The apparatus as recited in claim 2 , wherein, based at least in part on the determination that the first memory request comprises the first indication, the circuitry is further configured to prevent data prefetching into a cache using the target address of the first memory request.
4. The apparatus as recited in claim 1 , wherein the first memory request is a memory request that lacks one or more of temporal locality and spatial locality.
5. The apparatus as recited in claim 1 , wherein the circuitry is further configured to:
receive a third memory request; and
set a limit, in a cache, on one or more of storage time and storage location in the cache regarding data retrieved from lower-level memory into the cache during processing of the third memory request.
6. The apparatus as recited in claim 5 , wherein the circuitry is further configured to determine that the third memory request is a prefetch hint instruction comprising a third indication specifying setting the limit.
7. A method comprising:
receiving, by circuitry, a first memory request targeting a non-cache storage buffer;
preventing, by the circuitry, data prefetching into the non-cache storage buffer based at least in part on the first memory request;
receiving a second memory request targeting the non-cache storage buffer;
determining that the second memory request comprises an indication specifying that data prefetching is allowed using a target address of the first memory request; and
allowing data prefetching into the non-cache storage buffer based at least in part on the second memory request.
8. The method as recited in claim 7 , further comprising preventing, by the circuitry, data prefetching into the non-cache storage buffer based at least in part on the first memory request, responsive to the first memory request comprising a first indication specifying that data prefetching is prevented using a target address of the first memory request.
9. The method as recited in claim 8 , wherein in response to determining that the first memory request comprises the first indication, the method further comprises preventing data prefetching into a cache using the target address of the first memory request.
10. The method as recited in claim 7 , further comprising:
receiving a third memory request; and
setting a limit, in a cache, on one or more of storage time and storage location in the cache regarding data retrieved from lower-level memory into the cache during processing of the third memory request.
11. The method as recited in claim 10 , further comprising determining that the third memory request is a prefetch hint instruction comprising a third indication specifying setting the limit.
12. A processing unit comprising:
a processor core comprising a non-cache storage buffer; and
circuitry configured to:
receive a first memory request targeting the non-cache storage buffer;
prevent data prefetching into the non-cache storage buffer based at least in part on the first memory request, based at least in part on the first memory request comprising a first indication that data prefetching is prevented using a target address of the first memory request;
receive a second memory request targeting the non-cache storage buffer; and
allow data prefetching into the non-cache storage buffer based at least in part on the second memory request.
13. The processing unit as recited in claim 12 , wherein the circuitry is further configured to determine that the second memory request comprises a second indication specifying that data prefetching is allowed using a target address of the first memory request.