Real time generation of differential serial bus traffic

1. A method of real time generation of substantially continuous differential serial bus transmission using stored sequences of energy-representative packets, comprising:

at a controller, causing a non-volatile memory to start transmitting packets from a first sequence of packets comprising data representative of energy levels of a first differential signal of a serial bus and a second sequence of packets comprising data representative of energy levels of a second differential signal of the serial bus;

at the controller, receiving the transmitted packets from the first and second packet sequences and storing the received packets in a dual port random access memory (DPRAM);

at the controller, retrieving the stored packets from the DPRAM and providing the retrieved packets to a decoder;

at the controller, in response to DPRAM operation indicative of an approaching overflow condition, causing the non-volatile memory to stop transmitting packets from the first and second packet sequences, and in response to DPRAM operation indicative of an approaching underflow condition, causing the non-volatile memory to start transmitting packets from the first and second packet sequences;

wherein the decoder is configured to decode the first and second packet sequences to retrieve thereby data traffic associated with the data packet sequences and suitable for use by a serial bus encoder/transmitter for generating a differential serial bus transmission signal representative of the data traffic;

wherein the controller is configured to determine an approaching overflow condition comprising a difference between current input and output addresses being less than a first threshold value; and

wherein the first threshold value comprises a fixed address difference value that is large enough to provide sufficient time for the controller to cause the non-volatile memory to stop transmitting packets from the first and second packet sequences to avoid a buffer overflow.

2. The method of claim 1 , wherein the DPRAM is configured for storing packets thereto at a first rate and retrieving packets therefrom at a second rate, the second rate being slower than the first rate.

3. The method of claim 1 , wherein the controller is configured to store packets at DPRAM input addresses and retrieve packets from DPRAM output addresses, and wherein DPRAM operation indicative of an approaching overflow condition comprises a difference between current input and output addresses being less than a first threshold value.

4. The method of claim 1 , wherein the first threshold value comprises the difference between the write and the read addresses for the DPRAM.

5. The method of claim 1 , wherein the controller is configured to store packets at DPRAM input addresses and retrieve packets from DPRAM output addresses, and wherein DPRAM operation indicative of an underflow condition comprises a difference between current input and output addresses being greater than a second threshold value.

6. The method of claim 5 , wherein the second threshold value comprises a fixed address difference that is large enough to provide sufficient time for the controller to cause the non-volatile memory to start transmitting packets from the first and second packet sequences.

7. The method of claim 1 , wherein the transmitted packets from the first and second packet sequences are of a smaller bit width than a bit width of the DPRAM, and storing the received packets in the DPRAM further comprises:

packing a plurality of received packets into a word having a bit width substantially similar to that of the DPRAM; and

storing the transmitted packets from the first and second packet sequences as a sequence of packed words.

8. The method of claim 7 , wherein providing the retrieved packets to the decoder further comprises:

unpacking the plurality of transmitted packets from each packet retrieved from the DPRAM, providing the unpacked packets to the decoder.

9. The method of claim 8 , wherein the transmitted packets from the first and second packet sequences comprise 4-bit packets, and the bit width of the DPRAM is 32 bits.

10. Apparatus for real time generation of a differential serial bus transmission using stored sequences of energy-representative packets, comprising:

a controller, configured for causing a non-volatile memory to start transmitting packets from a first sequence of packets comprising data representative of energy levels of a first differential signal of a serial bus and a second sequence of packets comprising data representative of energy levels of a second differential signal of the serial bus;

the controller further configured for receiving the transmitted packets from the first and second packet sequences and storing the received packets in a dual port random access memory (DPRAM);

the controller further configured for retrieving the stored packets from the DPRAM and providing the retrieved packets to a decoder;

the controller further configured for causing the non-volatile memory to stop transmitting packets from the first and second packet sequences in response to DPRAM operation indicative of an approaching overflow condition;

the controller further configured for causing the non-volatile memory to start transmitting packets from the first and second packet sequences in response to DPRAM operation indicative of an approaching underflow condition;

wherein the decoder is configured to decode the first and second packet sequences to retrieve thereby data traffic associated with the data packet sequences and suitable for use by a serial bus encoder/transmitter for generating a differential serial bus transmission signal representative of the data traffic.

11. The apparatus of claim 10 , wherein the DPRAM is configured for storing packets thereto at a first rate and retrieving packets therefrom at a second rate, the second rate being slower than the first rate.

12. The apparatus of claim 10 , wherein the controller is configured to store packets at DPRAM input addresses and retrieve packets from DPRAM output addresses, and wherein DPRAM operation indicative of an approaching overflow condition comprises a difference between current input and output addresses being less than a first threshold value.

13. The apparatus of claim 12 , wherein the first threshold value comprises a fixed address difference value that is large enough to provide sufficient time for the controller to cause the non-volatile memory to stop transmitting packets from the first and second packet sequences.

14. The apparatus of claim 10 , wherein the controller is configured to store packets at DPRAM input addresses and retrieve packets from DPRAM output addresses, and wherein DPRAM operation indicative of an underflow condition comprises a difference between current input and output addresses being greater than a second threshold value.

15. The apparatus of claim 14 , wherein the second threshold value comprises a fixed address difference that is large enough to provide sufficient time for the controller to cause the non-volatile memory to start transmitting packets from the first and second packet sequences.

16. The apparatus of claim 10 , wherein the transmitted packets from the first and second packet sequences are of a smaller bit width than a bit width of the DPRAM, and storing the received packets in the DPRAM further comprises:

packing a plurality of received packets into a word having a bit width substantially similar to that of the DPRAM; and

storing the transmitted packets from the first and second packet sequences as a sequence of packed words.

17. The apparatus of claim 16 , wherein providing the retrieved packets to the decoder further comprises:

unpacking the plurality of transmitted packets from each packet retrieved from the DPRAM, providing the unpacked packets to the decoder.

18. The apparatus of claim 17 , wherein the transmitted packets from the first and second packet sequences comprise 4-bit packets, and the bit width of the DPRAM is 32 bits.