IP Library Granted Patent US 11,652,115
Granted Patent B2
US 11,652,115 · App. 16/758,537 · Granted May 16, 2023

Solid-state imaging device and electronic apparatus

Inventors: Tetsuya Uchida (Kanagawa, JP); Ryoji Suzuki (Kanagawa, JP); Yoshiharu Kudoh (Kanagawa, JP); Hiroyuki Mori (Kanagawa, JP); Harumi Tanaka (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/1461H01L27/1463H01L27/1464H01L27/14621H01L27/14623H01L27/14627H01L27/14634H01L27/14636H01L27/14645H01L27/14685H01L27/14689
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Quick Facts
Patent No.
US 11,652,115
App. No.
16/758,537
Granted
May 16, 2023
Kind
B2
Abstract

The present technology relates to a solid-state imaging device capable of suppressing deterioration in dark characteristics, and an electronic apparatus. The present invention is provided with: a photoelectric conversion section that performs photoelectric conversion; a charge retaining section that temporarily retains electric charge converted by the photoelectric conversion section; and a first trench formed in a semiconductor substrate between the photoelectric conversion section and the charge retaining section, the first trench being higher than the photoelectric conversion section in a depth direction of the semiconductor substrate. Alternatively, the first trench is lower than the photoelectric conversion section and higher than the charge retaining section in the depth direction of the semiconductor substrate. The present technology can be applied to, for example, a back-illuminated CMOS image sensor.

Claims (35)

1. A solid-state imaging device, comprising:

a photoelectric conversion section that performs photoelectric conversion;

a charge retaining section that temporarily retains electric charge converted by the photoelectric conversion section; and

dual first trenches formed in a semiconductor substrate between the photoelectric conversion section and the charge retaining section,

wherein the dual first trenches are higher than the photoelectric conversion section in a depth direction of the semiconductor substrate, and

wherein the dual first trenches are lower than the charge retaining section in the depth direction of the semiconductor substrate.

2. The solid-state imaging device according to claim 1 , further comprising a read gate that reads electric charge from the photoelectric conversion section,

wherein the read gate is formed to extend in a vertical direction and in a horizontal direction with respect to the photoelectric conversion section.

3. The solid-state imaging device according to claim 2 , further comprising a transfer gate that transfers the electric charge read by the read gate to the charge retaining section.

4. The solid-state imaging device according to claim 1 , further comprising:

a second trench formed in each of pixels adjacent to each other, the second trench penetrating the semiconductor substrate in the depth direction; and

a PN junction region that is formed on a sidewall of the second trench and that includes a P-type region and an N-type region.

5. The solid-state imaging device according to claim 4 , wherein the second trench is formed in a device isolation region.

6. The solid-state imaging device according to claim 4 , wherein the dual first trenches and the second trench are filled with a material that shields light.

7. The solid-state imaging device according to claim 1 , wherein the dual first trenches are formed at a position parallel to a long side of the charge retaining section.

8. The solid-state imaging device according to claim 1 , wherein each trench of the dual first trenches has a same configuration or a different configuration as the other trench of the dual first trenches.

9. An electronic apparatus, comprising:

an optical system;

a solid-state imaging device that receives light from the optical system, the solid-state imaging device including:

a photoelectric conversion section that performs photoelectric conversion;

a charge retaining section that temporarily retains electric charge converted by the photoelectric conversion section; and

dual first trenches formed in a semiconductor substrate between the photoelectric conversion section and the charge retaining section,

wherein the dual first trenches are higher than the photoelectric conversion section in a depth direction of the semiconductor substrate, and

wherein the dual first trenches are lower than the charge retaining section in the depth direction of the semiconductor substrate; and

a digital signal processor that processes signals received from the solid-state imaging device.

10. The electronic apparatus according to claim 9 , further comprising a read gate that reads electric charge from the photoelectric conversion section,

wherein the read gate is formed to extend in a vertical direction and in a horizontal direction with respect to the photoelectric conversion section.

11. The electronic apparatus according to claim 10 , further comprising a transfer gate that transfers the electric charge read by the read gate to the charge retaining section.

12. The electronic apparatus according to claim 9 , further comprising:

a second trench formed in each of pixels adjacent to each other, the second trench penetrating the semiconductor substrate in the depth direction; and

a PN junction region that is formed on a sidewall of the second trench and that includes a P-type region and an N-type region.

13. The electronic apparatus according to claim 12 , wherein the second trench is formed in a device isolation region.

14. The electronic apparatus according to claim 12 , wherein the dual first trenches and the second trench are filled with a material that shields light.

15. The electronic apparatus according to claim 9 , wherein the dual first trenches are formed at a position parallel to a long side of the charge retaining section.

16. The electronic apparatus according to claim 9 , wherein each trench of the dual first trenches has a same configuration or a different configuration as the other trench of the dual first trenches.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2020
From: UCHIDA, TETSUYA; SUZUKI, RYOJI; KUDOH, YOSHIHARU; MORI, HIROYUKI; TANAKA, HARUMI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 053443/0816 →
Priority Claims (3)
JP JP2017-216078 · Nov 9, 2017 · national
JP JP2018-190802 · Oct 9, 2018 · national
JP JP2018-208680 · Nov 6, 2018 · national
Continuity (1)
Related Publication 20200266221A1 · Aug 20, 2020