Driving circuit and display including the same

1. A driving circuit including a plurality of stages for supplying a plurality of signals,

wherein the respective stages include:

a first LTPO transistor including a first transistor that is a low-temperature polycrystalline silicon thin film transistor (LTPS TFT) and a second transistor that is an oxide TFT; and

a second LTPO transistor including a third transistor that is an LTPS TFT and a fourth transistor that is an oxide TFT, and

a first end of the first LTPO transistor is connected to a gate of the second LTPO transistor, and voltages of signals corresponding to the respective stages from among the signals are a voltage at a first end of the second LTPO transistor,

wherein a first end of the third transistor and a first end of the fourth transistor are connected to a first end of the second LTPO transistor, and a first voltage is supplied to a second end of the third transistor, while a clock signal is supplied to a second end of the fourth transistor.

2. The driving circuit of claim 1 , wherein

the respective stages further include:

a fifth transistor operable by a previous signal output from a previous stage of the respective stages; and

a sixth transistor operable by a next signal output from a next stage of the respective stages, and

the previous signal is supplied to a gate and a first end of the fifth transistor, the next signal is supplied to a gate of the sixth transistor, and a second end of the fifth transistor and a first end of the sixth transistor are connected to a gate of the first LTPO transistor.

3. The driving circuit of claim 1 , wherein

a first end of the first transistor and a first end of the second transistor are connected to a first end of the first LTPO transistor, and

a second voltage is supplied to a second end of the first transistor, while a third voltage is supplied to a second end of the second transistor.

4. The driving circuit of claim 1 , wherein

the respective stages further include: a control circuit including

a third LTPO transistor including a fifth transistor that is an LTPS TFT and a sixth transistor that is an oxide TFT; and

a fourth LTPO transistor including a seventh transistor that is an LTPS TFT and an eighth transistor that is an oxide TFT, and

a first end of the third LTPO transistor is connected to a gate of the fourth LTPO transistor, a voltage at a first end of the fourth LTPO is a voltage of a control signal that is an output of the control circuit, and the first LTPO transistor is operated according to the control signal.

5. The driving circuit of claim 4 , wherein

the control circuit of the respective stages further includes:

a ninth transistor operable by a previous control signal output from a control circuit of a previous stage of the respective stages; and

a tenth transistor operable by a next control signal output from a control circuit of a next stage of the respective stages, and

the previous control signal is supplied to a gate and a first end of the ninth transistor, the next control signal is supplied to a gate of the tenth transistor, and a second end of the ninth transistor and a first end of the tenth transistor are connected to a gate of the third LTPO transistor.

6. The driving circuit of claim 4 , wherein

a first end of the seventh transistor and a first end of the eighth transistor are connected to a first end of the fourth LTPO transistor, and

a first voltage is supplied to a second end of the seventh transistor, while a clock signal is supplied to a second end of the eighth transistor.

7. The driving circuit of claim 6 , wherein

a first end of the fifth transistor and a first end of the sixth transistor are connected to the first end of the third LTPO transistor, and

a second voltage is supplied to a second end of the fifth transistor, while a third voltage is supplied to a second end of the sixth transistor.

8. The driving circuit of claim 4 , wherein

the respective stages further include:

a ninth transistor operable by a corresponding one of a plurality of other signals corresponding to the signals; and

a tenth transistor operable by the control signal, and

the corresponding other signal is supplied to a gate and a first end of the ninth transistor, the control signal is supplied to a gate of the tenth transistor, and a second end of the ninth transistor and a first end of the tenth transistor are connected to a gate of the first LTPO transistor.

9. The driving circuit of claim 4 , wherein

a first end of the seventh transistor and a first end of the eighth transistor are connected to a first end of the second LTPO transistor, and

a first voltage is supplied to a second end of the seventh transistor, while a second voltage is supplied to a second end of the eighth transistor.

10. The driving circuit of claim 9 , wherein

a first end of the fifth transistor and a first end of the sixth transistor are connected to a first end of the first LTPO transistor, and

a third voltage is supplied to a second end of the fifth transistor, while the second voltage is supplied to a second end of the sixth transistor.

11. The driving circuit of claim 1 , wherein

a gate of the first transistor and a bottom gate of the second transistor extend from one line, and a top gate of the second transistor is connected to the bottom gate through a via contact.

12. The driving circuit of claim 1 , wherein

a gate of the third transistor and a bottom gate of the fourth transistor are branched from one line, and a top gate of the second transistor is connected to the bottom gate through a via contact.

13. A display comprising:

a plurality of pixel rows including a plurality of pixels; and

a gate driver including a plurality of stages for generating a plurality of gate signals and supplying the same to the pixel rows,

wherein the respective stages include a first LTPO transistor realized with a first transistor that is a low-temperature polycrystalline silicon thin film transistor (LTPS TFT) and a second transistor that is an oxide TFT, the second transistor is synchronized with an On-pulse of a corresponding previous gate signal and outputs a corresponding clock signal as the gate signal, and the first transistor is synchronized with an On-pulse of a corresponding next gate signal and outputs an Off-level gate signal, and

wherein

the respective stages further include a second LTPO transistor realized with a third transistor that is an LTPS TFT and a fourth transistor that is an oxide TFT,

the third transistor is synchronized with an On-pulse of the previous gate signal and turns on the second transistor, and

the fourth transistor is synchronized with an On-pulse of the corresponding next gate signal and turns on the first transistor.

14. The display of claim 13 , further comprising

a light emitting driver including a plurality of light emitting stages for generating a plurality of light emitting signals and supplying the same to the pixel rows,

wherein the respective light emitting stages include a second LTPO transistor realized with a third transistor that is an LTPS TFT and a fourth transistor that is an oxide TFT, the fourth transistor is synchronized with an On-pulse of a corresponding gate signal and outputs an On-level light emitting signal, and the third transistor is synchronized with an On-pulse of a light emitting control signal and outputs an Off-level light emitting signal.

15. The display of claim 14 , wherein

the respective light emitting stages further include a third LTPO transistor realized with a fifth transistor that is an LTPS TFT and a sixth transistor that is an oxide TFT,

the fifth transistor is synchronized with an On-pulse of the corresponding gate signal and turns on the fourth transistor, and

the sixth transistor is synchronized with an On-pulse of the light emitting control signal and turns on the third transistor.

16. The display of claim 14 , wherein

the respective light emitting stages further include a light emitting control circuit for generating the light emitting control signal,

the light emitting control circuit includes:

a fourth LTPO transistor including a fifth transistor that is an LTPS TFT and a sixth transistor that is an oxide TFT; and

a fifth LTPO transistor including a seventh transistor that is an LTPS TFT and an eighth transistor that is an oxide TFT, and

a first end of the fourth LTPO transistor is connected to a gate of the fifth LTPO transistor, while a voltage at a first end of the fifth LTPO is a voltage of the control signal.

17. A driving circuit including a plurality of stages for supplying a plurality of signals,

wherein the respective stages include:

a first LTPO transistor including a first transistor that is a low-temperature polycrystalline silicon thin film transistor (LTPS TFT) and a second transistor that is an oxide TFT;

a second LTPO transistor including a third transistor that is an LTPS TFT and a fourth transistor that is an oxide TFT;

a fifth transistor operable by a previous signal output from a previous stage of the respective stages; and

a sixth transistor operable by a next signal output from a next stage of the respective stages, and

wherein

a first end of the first LTPO transistor is connected to a gate of the second LTPO transistor,

voltages of signals corresponding to the respective stages from among the signals are a voltage at a first end of the second LTPO transistor,

the previous signal is supplied to a gate and a first end of the fifth transistor, the next signal is supplied to a gate of the sixth transistor, and

a second end of the fifth transistor and a first end of the sixth transistor are connected to a gate of the first LTPO transistor.