Method and structure to reduce cell width in semiconductor device
A semiconductor device includes a dielectric layer having a first surface and a second surface opposite to the first surface; an active region on the first surface of the dielectric layer; a power rail under the second surface of the dielectric layer, wherein the dielectric layer is between the active region and the power rail; a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer; an intermediate layer comprising: first and second conductive segments; and wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment, wherein a join length between the first conductive segment and the spacer is equal to a join length between the second conductive segment and the spacer.
1. A semiconductor device, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface;
an active region on the first surface of the dielectric layer;
a power rail under the second surface of the dielectric layer, wherein the dielectric layer is between the active region and the power rail;
a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer;
an intermediate layer comprising:
a first conductive segment and a second conductive segment; and
wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment,
wherein a join length between the first conductive segment and the spacer is equal to a join length between the second conductive segment and the spacer.
2. The semiconductor device according to claim 1 , wherein the power rail is coupled to the first conductive segment.
3. The semiconductor device according to claim 2 , wherein the active region overlaps with the power rail.
4. The semiconductor device according to claim 1 , wherein the intermediate layer is over the dielectric layer, and the active region is between the intermediate layer and the dielectric layer.
5. The semiconductor device according to claim 4 , wherein the intermediate layer is between a metal layer and the active region.
6. The semiconductor device according to claim 5 , wherein the intermediate layer is in an inter layer dielectric layer over the first surface of the dielectric layer.
7. The semiconductor device according to claim 6 , wherein the metal layer extends above the inter layer dielectric layer and the intermediate layer.
8. The semiconductor device according to claim 1 , wherein the first conductive segment and the second conductive segment are leveled with each other.
9. The semiconductor device according to claim 1 , wherein the spacer is in contact with the first surface of the dielectric layer.
10. The semiconductor device according to claim 1 , further comprising:
a gate-strip over the dielectric layer, wherein the first conductive segment is between the gate-strip and the spacer.
11. A semiconductor device, comprising:
a dielectric layer;
an active region on the dielectric layer;
a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer;
a first transistor in the first part of the active region;
a second transistor in the second part of the active region;
a first conductive segment and a second conductive segment associated with the first transistor and the second transistor, respectively, wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment; and
a power rail being overlapped with the active region.
12. The semiconductor device according to claim 11 , further comprising:
a first gate-strip covering a channel region of the first transistor, wherein the power rail is overlapped with the channel region of the first transistor.
13. The semiconductor device according to claim 12 , wherein the first conductive segment is disposed over a doped region, immediately adjacent to the channel region of the first transistor, of the first transistor, and the second conductive segment is disposed over a doped region, immediately adjacent to the channel region of the second transistor, of the second transistor, wherein the power rail is overlapped with the doped region of the first transistor and the doped region of the second transistor.
14. The semiconductor device according to claim 11 , wherein the dielectric layer has a first surface and a second surface opposite to each other,
wherein the active region is disposed on the first surface of the dielectric layer, and the power rail is disposed under the second surface of the dielectric layer.
15. The semiconductor device according to claim 14 , wherein the first conductive segment and the second conductive segment are in an intermediate layer,
wherein the intermediate layer is over the dielectric layer, and the active region is between the intermediate layer and the dielectric layer.
16. The semiconductor device according to claim 15 , wherein the active region is between the intermediate layer and the power rail.
17. The semiconductor device according to claim 16 , further comprising:
a first cell having at least one logic function;
a second cell having at least one logic function; and
wherein the first transistor is located inside the first cell and the second transistor is located inside the second cell.
18. The semiconductor device according to claim 17 , wherein the spacer is located at a boundary separating the first cell from the second cell.
19. The semiconductor device according to claim 16 , further comprising:
a cell having at least one logic function,
wherein the first transistor, the second transistor and the spacer are located in the cell.
20. A method of generating, by a processor, a layout design of a semiconductor device, the method comprising:
creating an active region pattern, extending in a first direction, that specifies an active region in a semiconductor substrate;
creating two intermediate layer patterns, extending in a second direction perpendicular to the first direction for a same extension length, over the active region pattern, wherein the two intermediate layer patterns specify two conductive segments in an intermediate layer, wherein the intermediate layer is a layer between the active region and a metal layer, with the metal layer overlying an inter layer dielectric layer on a channel region;
creating a spacer pattern, extending in the second direction, jointing the two intermediate layer patterns, and dividing the active region pattern into a first part and a second part, wherein the spacer pattern specifies a spacer that conductively isolates the two conductive segments from each other in the intermediate layer and conductively isolates the first part of the active region from the second part of the active region in the semiconductor substrate;
creating a power rail pattern overlapping with the active region pattern, wherein the power rail pattern specifies a power rail coupled to the two conductive segments; and
manufacturing the semiconductor device according to the layout design.