Three-dimensional semiconductor memory device

1. A three-dimensional semiconductor memory device, comprising:

a peripheral circuit structure including a plurality of first metal pads; and

a cell array structure disposed on the peripheral circuit structure and including a plurality of second metal pads,

wherein the peripheral circuit structure comprises:

a first substrate including a first peripheral circuit region and a second peripheral circuit region;

a peripheral circuit on the first substrate; and

a first passive device electrically connected to the peripheral circuit,

wherein the cell array structure comprises:

a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the peripheral circuit structure, respectively;

gate electrodes stacked on the cell array region and the contact region of the second substrate and disposed between the peripheral circuit structure and the second substrate of the cell array structure; and

cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes,

wherein the plurality of first metal pads comprises first pads and second pads,

wherein the first pads of the plurality of first metal pads electrically connected to the plurality of second metal pads, and

wherein the first passive device consists of the second pads of the plurality of first metal pads.

2. The device of claim 1 , wherein the cell array structure further comprises:

a first contact line disposed on the first passive device and contacting a first surface of the first passive device; and

second contact lines on the cell contact plugs,

wherein the second contact lines electrically connect the peripheral circuit structure and the cell array structure to each other, and

wherein the first contact line is electrically connected to the peripheral circuit and is electrically disconnected from the second substrate, and

wherein a part of the first passive device consists of the first contact line.

3. The device of claim 2 , wherein the cell array structure further comprises vias contacting the first contact line.

4. The device of claim 2 , wherein the first passive device is disposed on the first peripheral circuit region, and

wherein the plurality of second metal pads are electrically connected to the cell contact plugs.

5. The device of claim 4 , wherein the first pads of the plurality of first metal pads and the plurality of second metal pads are connected by bonding manner.

6. The device of claim 1 , wherein the first passive device is connected to at least two contact plugs.

7. The device of claim 1 , wherein the first passive device constitutes a resistor.

8. The device of claim 1 , wherein the first passive device constitutes electrodes of a capacitor.

9. The device of claim 1 , wherein the peripheral circuit structure further comprises:

first contact plugs on the first peripheral circuit region of the first substrate;

second contact plugs on the second peripheral circuit region of the first substrate; and

first contact lines on the first contact plugs,

wherein the cell array structure further comprises second contact lines on the cell contact plugs, and

wherein the first contact lines contact the second contact lines.

10. The device of claim 1 , wherein the peripheral circuit structure further comprises:

first contact plugs on the first peripheral circuit region of the first substrate;

second contact plugs on the second peripheral circuit region of the first substrate; and

first contact lines on the second contact plugs,

wherein the first passive device is vertically between the gate electrodes and the second contact plugs and includes the first contact lines.

11. The device of claim 1 , wherein the first substrate further comprises a third peripheral circuit region,

wherein the second substrate further comprises an outer region, which vertically overlaps with the third peripheral circuit region and is exposed by the gate electrodes, and a common source region, which is disposed in the outer region of the second substrate,

wherein the peripheral circuit structure further comprises:

first contact plugs on the first peripheral circuit region of the first substrate;

second contact plugs on the second peripheral circuit region of the first substrate; and

first contact lines on the first contact plugs,

wherein the cell array structure further comprises:

common source contacts on the outer region of the second substrate; and

second contact lines, which are disposed on the common source contacts and are connected to the common source contacts, and

wherein the second contact lines are misaligned with the first contact lines, when viewed in a plan view.

12. The device of claim 11 , wherein the first contact lines constitute a passive device, and

the second contact lines are connected to a driving device configured to apply a voltage to the common source region.

13. The device of claim 1 , wherein the gate electrodes comprise a first gate electrode and a second gate electrode on the first gate electrode,

the three-dimensional semiconductor memory device further comprises a vertical channel portion, which is disposed on the cell array region of the second substrate to penetrate the gate electrodes,

the vertical channel portion comprises a first portion, which penetrates the first gate electrode, and a second portion, which is disposed on the first portion to penetrate the second gate electrode, and

a sidewall of the first portion is misaligned with a sidewall of the second portion.

14. A three-dimensional semiconductor memory device, comprising:

a peripheral circuit structure including a plurality of first metal pads; and

a cell array structure disposed on the peripheral circuit structure and including a plurality of second metal pads,

wherein the peripheral circuit structure comprises:

a first substrate including a first peripheral circuit region and a second peripheral circuit region;

first contact plugs on the first peripheral circuit region of the first substrate; and

second contact plugs on the second peripheral circuit region of the first substrate;

wherein the cell array structure comprises:

a second substrate including a cell array region, a contact region, and an outer region, the cell array region vertically overlapping the second peripheral circuit region and the contact region vertically overlapping the first peripheral circuit region;

gate electrodes stacked on the cell array region and the contact region of the second substrate and disposed between the peripheral circuit structure and the second substrate of the cell array structure;

cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes and connected to the first contact plugs;

a common source region disposed in the outer region of the second substrate; and

a first passive device electrically connected to the common source region, wherein the first passive device consists of the plurality of second metal pads.

15. The device of claim 14 , wherein a part of the first passive device consists of the plurality of first metal pads.

16. The device of claim 14 , wherein the peripheral circuit structure further comprises

a first contact line disposed on the first passive device; and

vias contacting the first contact line.

17. The device of claim 14 , wherein the first passive device constitutes a resistor.

18. The device of claim 14 , wherein the first passive device constitutes electrodes of a capacitor.

19. The device of claim 14 , wherein the first passive device is connected to at least two contact plugs.

20. The device of claim 14 , wherein the gate electrodes comprise a first gate electrode and a second gate electrode on the first gate electrode,

the three-dimensional semiconductor memory device further comprises a vertical channel portion, which is disposed on the cell array region of the second substrate to penetrate the gate electrodes,

the vertical channel portion comprises a first portion, which penetrates the first gate electrode, and a second portion, which is disposed on the first portion to penetrate the second gate electrode, and

a sidewall of the first portion is misaligned with a sidewall of the second portion.