P-type field effect transistor and method for fabricating the same

1. A method for fabricating a p-type field effect transistor (pFET), comprising:

providing a substrate;

performing an ion implantation process to implant germanium (Ge) into the substrate to form a channel region, wherein the channel region comprises silicon germanium (SiGe), a concentration of germanium is between 5×10 13 ions/cm 2 to 1×10 17 ions/cm 2 , an energy of the ion implantation process is between 0.5 KeV to 20 KeV, and a temperature of the ion implantation process is between 0° C. to 120° C.;

performing an anneal process to divide the channel region into a top portion and a bottom portion, wherein after the anneal process, the channel region comprises only a single p-type dopant, wherein the top portion and the bottom portion of the channel region is made of SiGe, and wherein a depth of the top portion is equal to a depth of the bottom portion; and

forming a gate structure on the substrate.

2. The method of claim 1 , further comprising:

forming a pad layer on the substrate; and

forming a well in the substrate before performing the ion implantation process.

3. The method of claim 2 , wherein the pad layer comprises silicon oxide.

4. The method of claim 2 , further comprising removing the pad layer after performing the anneal process.

5. The method of claim 4 , further comprising:

forming the gate structure on the substrate after removing the pad layer; and

forming a lightly doped drain adjacent to two sides of the gate structure;

wherein the depth of the channel region is less than a depth of the lightly doped drain.

6. The method of claim 1 , further comprising forming a well in the substrate after performing the ion implantation process.