Array substrate, fabrication method for array substrate, and display panel
View Patent ↗Embodiments of the present application provide an array substrate, a fabrication method for an array substrate, and a display panel. The array substrate includes a substrate, a gate, a gate insulating layer, a seed layer, and a semiconductor layer that are sequentially stacked. A surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains, which enhances light absorption of the semiconductor layer and solves the problems of poor light sensitivity and slow response speed of semiconductor devices.
1. An array substrate, comprising:
a substrate, wherein the substrate comprises a first surface and a second surface that are disposed oppositely to each other;
a gate, wherein the gate partially covers the first surface;
a gate insulating layer, wherein the gate insulating layer is disposed on a side of the gate away from the first surface and extends to the first surface;
a seed layer, wherein the seed layer is disposed on a side of the gate insulating layer away from the gate;
a semiconductor layer, wherein the semiconductor layer partially covers a side of the seed layer away from the gate insulating layer, and a surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains; and
a source and a drain, wherein the source and the drain are disposed in a region of the seed layer not covered by the semiconductor layer, and the source and the drain are respectively disposed on both sides of the semiconductor layer perpendicular to the first surface.
2. The array substrate according to claim 1 , wherein the semiconductor layer comprises a crystalline layer and a conductive layer; the crystalline layer partially covers the side of the seed layer away from the gate insulating layer; a surface of the crystalline layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains; the conductive layer is correspondingly disposed on a side of the crystal layer away from the seed layer; and the conductive layer has a concave-convex structure.
3. The array substrate according to claim 2 , wherein the concave-convex structure is of any one of an irregular pulse shape, a sawtooth shape, a wave shape, and a broken line shape.
4. The array substrate according to claim 2 , wherein a carrier concentration of the crystalline layer is higher than a carrier concentration of the conductive layer.
5. The array substrate according to claim 4 , wherein a thickness of the crystalline layer is 5 nm to 50 nm.
6. The array substrate according to claim 2 , wherein a material of the crystalline layer is zinc oxide (ZnO), silver (Ag), carbon (C), or a combination thereof.
7. The array substrate according to claim 1 , wherein a material of the seed layer is a metal oxide, a metal, an alloy, or a combination thereof, and a thickness of the seed layer is 5 nm.
8. A fabrication method for an array substrate, comprising:
providing a substrate, wherein the substrate comprises a first surface and a second surface that are disposed oppositely to each other;
disposing a gate on the first surface, wherein the gate partially covers the first surface;
disposing a gate insulating layer on a side of the gate away from the first surface, wherein the gate insulating layer extends to the first surface;
disposing a seed layer on a side of the gate insulating layer away from the gate; and
disposing a semiconductor layer on a side of seed layer away from the gate insulating layer, wherein the semiconductor layer partially covers a side of the seed layer, and a surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains,
wherein disposing the seed layer on the side of the gate insulating layer away from the gate comprises depositing aluminum oxide as the seed layer using atomic layer deposition.
9. The fabrication method according to claim 8 , wherein disposing the semiconductor layer on the side of the seed layer away from the gate insulating layer comprises:
disposing a crystalline layer on a side of the seed layer away from the gate insulating layer, and the crystalline layer has a concave-convex structure on the surface of the side away from the seed layer formed by growth of nanocrystalline grains;
disposing a conductive layer on a side of the crystalline layer away from the seed layer, wherein the conductive layer has a concave-convex structure; and
performing etching to the crystalline layer and the conductive layer so that the crystalline layer and the conductive layer partially cover the seed layer to obtain the semiconductor layer.
10. The fabrication method according to claim 9 , wherein disposing the crystalline layer on the side of the seed layer away from the gate insulating layer is formed using a method of an atomic layer deposition, a chemical vapor deposition technique, a sol-gel method, or a sputtering method.
11. A display panel, comprising an array substrate, wherein the array substrate comprises:
a substrate, wherein the substrate comprises a first surface and a second surface that are disposed oppositely to each other;
a gate, wherein the gate partially covers the first surface;
a gate insulating layer, wherein the gate insulating layer is disposed on a side of the gate away from the first surface and extends to the first surface;
a seed layer, wherein the seed layer is disposed on a side of the gate insulating layer away from the gate;
a semiconductor layer, wherein the semiconductor layer partially covers a side of the seed layer away from the gate insulating layer, and a surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains; and
a source and a drain, wherein the source and the drain are disposed in a region of the seed layer not covered by the semiconductor layer, and the source and the drain are respectively disposed on both sides of the semiconductor layer perpendicular to the first surface.
12. The display panel according to claim 11 , wherein the semiconductor layer comprises a crystalline layer and a conductive layer; the crystalline layer partially covers the side of the seed layer away from the gate insulating layer, and a surface of the crystalline layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains;
and the conductive layer is correspondingly disposed on a side of the crystalline layer away from the seed layer, and the conductive layer has a concave-convex structure.
13. The display panel according to claim 12 , wherein the concave-convex structure is of any one of an irregular pulse shape, a sawtooth shape, a wave shape, and a broken line shape.
14. The display panel according to claim 12 , wherein a carrier concentration of the crystalline layer is higher than a carrier concentration of the conductive layer.
15. The display panel according to claim 14 , wherein a thickness of the crystalline layer is 5 nm to 50 nm.
16. The display panel according to claim 12 , wherein a material of the crystalline layer is zinc oxide (ZnO), silver (Ag), carbon (C), or a combination thereof.
17. The display panel according to claim 11 , wherein a material of the seed layer is a metal oxide, a metal, an alloy, or a combination thereof, and a thickness of the seed layer is 5 nm.