Self-calibrating timing generator
A timing generator includes a first current source, a first switch, a second current source, a second switch, a third switch, a capacitor, a signal synthesizer, and a timing difference extractor. The first current source is for generating a first current according to the input voltage. The second current source is for generating a second current according to the input voltage. The first switch includes a control terminal for receiving a charging signal. The second switch includes a control terminal for receiving a timing difference signal. The third switch includes a control terminal for receiving a reset signal. The capacitor is coupled between a charging terminal and a ground terminal. The signal synthesizer is for generating a timing signal according to a charging voltage and a reference voltage. The timing difference extractor is for generating a timing difference signal according to the timing signal and a deformed timing signal.
1. A timing generator comprising:
a first current source configured to generate a first current according to an input voltage;
a first switch, comprising:
a first terminal coupled to the first current source;
a second terminal coupled to a charging terminal; and
a control terminal configured to receive a charging signal;
a second current source configured to generate a second current according to the input voltage;
a second switch, comprising:
a first terminal coupled to the second current source;
a second terminal coupled to the charging terminal; and
a control terminal configured to receive a timing difference signal;
a third switch, comprising:
a first terminal coupled to the charging terminal;
a second terminal coupled to a ground terminal; and
a control terminal configured to receive a reset signal;
a capacitor coupled between the charging terminal and the ground terminal;
a signal synthesizer coupled to the charging terminal, and configured to generate a timing signal according to a charging voltage and a reference voltage; and
a timing difference extractor coupled to the signal synthesizer and the control terminal of the second switch, and configured to generate the timing difference signal according to the timing signal and a deformed timing signal.
2. The timing generator of claim 1 , wherein the signal synthesizer comprises:
a comparator, comprising:
a negative input terminal configured to receive the reference voltage;
a positive input terminal coupled to the charging terminal, and configured to receive a charging voltage; and
an output terminal; and
a latch, comprising:
a set terminal configured to receive the charging signal;
a reset terminal coupled to the output terminal of the comparator; and
an output terminal configured to output the timing signal.
3. The timing generator of claim 1 , wherein the timing difference extractor comprises:
a first input terminal coupled to an output terminal of the signal synthesizer;
a second input terminal configured to receive the deformed timing signal; and
an output terminal configured to output the timing difference signal.
4. The timing generator of claim 3 , wherein the timing difference extractor is an XOR gate.
5. The timing generator of claim 3 , wherein the timing difference extractor is an NOR gate.
6. The timing generator of claim 3 , wherein the timing difference extractor is an AND gate.
7. The timing generator of claim 1 , wherein:
the timing difference between the deformed timing signal and the timing signal is generated by an external circuit; and
a pulse width of the timing signal is greater than a pulse width of the timing difference signal.
8. The timing generator of claim 1 , wherein a current value of the first current is substantially equal to a current value of the second current.
9. The timing generator of claim 1 , wherein the first switch, the second switch and the third switch are N-type transistors.
10. A timing generator comprising:
a first current source configured to generate a first current according to an input voltage;
a first switch, comprising:
a first terminal coupled to the first current source;
a second terminal coupled to a charging terminal; and
a control terminal configured to receive a charging signal;
a second switch, comprising:
a first terminal coupled to a bias terminal;
a second terminal; and
a control terminal configured to receive a timing difference signal;
a second current source coupled to the second terminal of the second switch, and configured to generate a second current according to the input voltage;
a third switch, comprising:
a first terminal coupled to the charging terminal;
a second terminal coupled to a ground terminal; and
a control terminal configured to receive a reset signal;
a fourth switch, comprising:
a first terminal;
a second terminal coupled to the bias terminal; and
a control terminal configured to receive the reset signal;
a first capacitor coupled between the charging terminal and the ground terminal;
a second capacitor coupled between the bias terminal and the first terminal of the fourth switch;
a signal synthesizer coupled to the charging terminal, and configured to generate a timing signal according to a charging voltage and an offset reference voltage; and
a timing difference extractor coupled to the signal synthesizer and the control terminal of the second switch, and configured to generate the timing difference signal according to the timing signal and a deformed timing signal.
11. The timing generator of claim 10 , wherein the signal synthesizer comprises:
a comparator, comprising:
a negative input terminal coupled to the bias terminal, and configured to receive the offset reference voltage;
a positive input terminal coupled to the charging terminal, and configured to receive a charging voltage; and
an output; terminal; and
a latch, comprising:
a set terminal configured to receive the charging signal;
a reset terminal coupled to the output terminal of the comparator; and
an output terminal configured to output the timing signal.
12. The timing generator of claim 10 , wherein the timing difference extractor comprises:
a first input terminal coupled to an output terminal of the signal synthesizer;
a second input terminal configured to receive the deformed timing signal; and
an output terminal configured to output the timing difference signal.
13. The timing generator of claim 12 , wherein the timing difference extractor is an XOR gate.
14. The timing generator of claim 12 , wherein the timing difference extractor is an NOR gate.
15. The timing generator of claim 12 , wherein the timing difference extractor is an AND gate.
16. The timing generator of claim 10 , wherein:
the timing difference between the deformed timing signal and the timing signal is generated by an external circuit; and
a pulse width of the timing signal is greater than a pulse width of the timing difference signal.
17. The timing generator of claim 10 , wherein a current value of the first current is substantially equal to a current value of the second current.
18. The timing generator of claim 10 , wherein the first switch, the second switch, the third switch and the fourth switch are N-type transistors.