IP Library Granted Patent US 11,688,765
Granted Patent B2
US 11,688,765 · App. 17/198,334 · Granted Jun 27, 2023

Semiconductor device and method for manufacturing the same

Inventor: Yuhki Fujino (Kanazawa Ishikawa, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
H01L29/0653H01L29/0623H01L29/0696H01L29/66712H01L29/7802H01L29/7813
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Quick Facts
Patent No.
US 11,688,765
App. No.
17/198,334
Granted
Jun 27, 2023
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.

Claims (49)

1. A semiconductor device comprising:

a first electrode;

a first semiconductor region of a first conductivity type provided on the first electrode, and electrically connected to the first electrode;

a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region;

a third semiconductor region of the first conductivity type provided on another part of the first semiconductor region, the third semiconductor region including

a first region separated from the second semiconductor region in a second direction perpendicular to a first direction from the first electrode to the first semiconductor region, and

a second region provided between the first region and the second semiconductor region, an impurity concentration of the first conductivity type in the second region being higher than an impurity concentration of the first conductivity type in the first region;

a fourth semiconductor region of the second conductivity type provided on the second semiconductor region, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region;

a fifth semiconductor region of the first conductivity type provided on a part of the fourth semiconductor region;

a gate electrode facing the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region; and

a second electrode provided on the fourth semiconductor region and the fifth semiconductor region, the second electrode being electrically connected to the fourth semiconductor region and the fifth semiconductor region wherein,

an impurity concentration of the second conductivity type in the second semiconductor region is higher than an impurity concentration of the first conductivity type in the third semiconductor region, and

a length of the third semiconductor region in the second direction is longer than a length of the second semiconductor region in the second direction.

2. The device according to claim 1 , wherein the impurity concentration of the first conductivity type in the first region is less than 0.5 times the impurity concentration of the first conductivity type impurity in the second region.

3. The device according to claim 1 , wherein

the first region is separated from the second semiconductor region in the second direction and a third direction,

the third direction is perpendicular to the first direction and intersects the second direction, and

the second region is provided between the second semiconductor region and the first region in the second direction and the third direction.

4. The device according to claim 1 , further comprising an insulating part,

the second semiconductor region being provided around the insulating part in a second direction that is perpendicular to a first direction directed from the first electrode to the first semiconductor region.

5. A semiconductor device comprising:

a first electrode;

a first semiconductor region of a first conductivity type provided on the first electrode, and electrically connected to the first electrode;

a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region;

a third semiconductor region of the first conductivity type provided on another part of the first semiconductor region, the third semiconductor region including

a first region separated from the second semiconductor region in a second direction perpendicular to a first direction from the first electrode to the first semiconductor region, and

a second region provided between the first region and the second semiconductor region, an impurity concentration of the first conductivity type in the second region being higher than an impurity concentration of the first conductivity type in the first region;

a fourth semiconductor region of the second conductivity type provided on the second semiconductor region, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region;

a fifth semiconductor region of the first conductivity type provided on a part of the fourth semiconductor region;

an intermediate region of a first conductivity type provided between the first semiconductor region and the second semiconductor region, and between the first semiconductor region and the third semiconductor region, an impurity concentration of the first conductivity type in the intermediate region being lower than an impurity concentration of the first conductivity type in the first semiconductor region, the intermediate region including

a first portion provided between the first semiconductor region and the second semiconductor region, and between the first semiconductor region and the second region, and

a second portion provided between the first semiconductor region and the first region, an impurity concentration of the first conductivity type in the second portion being lower than an impurity concentration of the first conductivity type in the first portion;

a gate electrode facing the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region; and

a second electrode provided on the fourth semiconductor region and the fifth semiconductor region, the second electrode being electrically connected to the fourth semiconductor region and the fifth semiconductor region.

6. A semiconductor device comprising:

a first electrode;

a first semiconductor region of a first conductivity type provided on the first electrode, and electrically connected to the first electrode;

an intermediate region, an impurity concentration of the first conductivity type in the intermediate region being lower than an impurity concentration of the first conductivity type in the first semiconductor region,

the intermediate region including:

a first portion provided on a part of the first semiconductor region; and

a second portion provided on another part of the first semiconductor region, an impurity concentration of the first conductivity type in the second portion being lower than an impurity concentration of the first conductivity type in the first portion;

a second semiconductor region of a second conductivity type provided on a part of the first portion;

an insulating part, the second semiconductor region being provided around the insulating part in a second direction that is perpendicular to a first direction directed from the first electrode to the first semiconductor region;

a third semiconductor region of the first conductivity type provided on another part of the first portion and the second portion;

a fourth semiconductor region of the second conductivity type provided on the second semiconductor region, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region;

a fifth semiconductor region of the first conductivity type provided on the fourth semiconductor region;

a gate electrode facing the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region; and

a second electrode provided on the fourth semiconductor region and the fifth semiconductor region, the second electrode being electrically connected to the fourth semiconductor region and the fifth semiconductor region.

7. The device according to claim 6 , wherein the insulating part includes a gap.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2021
From: FUJINO, YUHKI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 056018/0228 →
Priority Claims (1)
JP JP2020-153233 · Sep 11, 2020 · national
Continuity (1)
Related Publication 20220085159A1 · Mar 17, 2022