Ceramic electronic component and method of manufacturing the same

1. A ceramic electronic component comprising:

a multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a pair of second multilayer structures respectively disposed on top and bottom faces of the first multilayer structure, the first multilayer structure including first dielectric layers and first internal electrode layers that are alternately stacked, each of the second multilayer structures including second dielectric layers and second internal electrode layers that are alternately stacked, the first and second dielectric layers being mainly composed of ceramic, the first internal electrode layers being formed so as to be alternately exposed to two edge faces opposite to each other of the multilayer chip, the second internal electrode layers being formed so as to be alternately exposed to the two edge faces; and

a pair of external electrodes respectively formed on the two edge faces, each of the external electrodes extending to at least one of side faces of the multilayer chip,

wherein a main component of each of the first internal electrode layers and a main component of each of the second internal electrode layers differ from a main component of each of the external electrodes,

wherein a width of each of the first internal electrode layers in a first direction orthogonal to a second direction and a third direction is greater than a width of each of the second internal electrode layers in the first direction, the second direction being a direction in which the first dielectric layers and the first internal electrode layers are stacked, the third direction being a direction in which the two edge faces are opposite to each other,

wherein in a first capacitance section where adjacent first internal electrode layers connected to different external electrodes are opposite to each other, the number of the first internal electrode layers per 1 mm of height in the second direction is 500 or greater, and

wherein in a second capacitance section where adjacent second internal electrode layers connected to different external electrodes are opposite to each other, the number of the second internal electrode layers per 1 mm of height in the second direction is 500 or greater.

2. The ceramic electronic component according to claim 1 , wherein a ratio of the width of each of the second internal electrode layers in the first direction to the width of each of the first internal electrode layers in the first direction is 0.5 to 0.75.

3. The ceramic electronic component according to claim 1 , wherein a ratio of the width of each of the second internal electrode layers in the first direction to the width of each of the first internal electrode layers in the first direction is 0.55 to 0.70.

4. The ceramic electronic component according to claim 1 , wherein a ratio of the width of each of the second internal electrode layers in the first direction to the width of each of the first internal electrode layers in the first direction is 0.60 to 0.65.

5. The ceramic electronic component according to claim 1 , wherein in a cross-section orthogonal to the third direction, in each of ridge portions, a shortest distance among distances between the ridge portion and the first internal electrode layers and distances between the ridge portion and the second internal electrode layers is 10 μm or greater, the ridge portions including first ridge portions each connecting the top face of the multilayer chip and a corresponding one of two side faces of the multilayer chip and second ridge portions each connecting the bottom face of the multilayer chip and a corresponding one of the two side faces of the multilayer chip.

6. The ceramic electronic component according to claim 1 , wherein 300 to 950 of the first internal electrode layers are included in the first multilayer structure, and 25 to 250 of the second internal electrode layers are included in each of the second multilayer structures.

7. The ceramic electronic component according to claim 1 , wherein the multilayer chip has a length of 1.6 mm or greater, a width of 0.8 mm or greater, and a height of 0.8 mm or greater.

8. The ceramic electronic component according to claim 1 , wherein the main component of each of the first internal electrode layers and the main component of the second internal electrode layers are nickel,

wherein the main component of each of the external electrodes is copper.

9. The ceramic electronic component according to claim 1 , wherein a thickness of each of the first and second dielectric layers is 1 μm or less.

10. A method of manufacturing a ceramic electronic component, comprising:

preparing a ceramic multilayer structure including a first multilayer portion and a pair of second multilayer portions respectively disposed on top and bottom faces of the first multilayer portion, the first multilayer portion including first ceramic dielectric green sheets and first patterns of metal conductive pastes that are alternately stacked so that the first patterns are exposed to two edge faces opposite to each other of the first multilayer portion, each of the second multilayer portions including second ceramic dielectric green sheets and second patterns of metal conductive pastes that are alternately stacked so that the second patterns are exposed to two edge faces opposite to each other of the second multilayer portion;

obtaining a multilayer chip by firing the ceramic multilayer structure, the multilayer chip having a substantially rectangular parallelepiped shape and including a first multilayer structure and a pair of second multilayer structures respectively disposed on top and bottom faces of the first multilayer structure, the first multilayer structure including first dielectric layers and first internal electrode layers that are alternately stacked, each of the second multilayer structures including second dielectric layers and second internal electrode layers that are alternately stacked, the first internal electrode layers being formed so as to be alternately exposed to two edge faces opposite to each other of the multilayer chip, the second internal electrode layers being formed so as to be alternately exposed to the two edge faces;

applying a pair of metal pastes respectively on the two edge faces of the multilayer chip, each of the metal pastes extending to at least one of side faces of the multilayer chip; and

baking the metal pastes to form a pair of external electrodes,

wherein a main component of each of the first internal electrode layers and a main component of each of the second internal electrode layers differ from a main component of each of the external electrodes,

wherein a width of each of the first internal electrode layers in a first direction orthogonal to a second direction and a third direction is greater than a width of each of the second internal electrode layers in the first direction, the second direction being a direction in which the first dielectric layers and the first internal electrode layers are stacked, the third direction being a direction in which the two edge faces are opposite to each other,

wherein in a first capacitance section where adjacent first internal electrode layers connected to different external electrodes are opposite to each other, the number of the first internal electrode layers per 1 mm of height in the second direction is 500 or greater, and

wherein in a second capacitance section where adjacent second internal electrode layers connected to different external electrodes are opposite to each other, the number of the second internal electrode layers per 1 mm of height in the second direction is 500 or greater.