Integrated circuit device including metal-oxide semiconductor transistors

1. An integrated circuit device, comprising:

an active region;

an active cutting region at a side of the active region in a first direction, the active cutting region separating the active region into separate parts;

a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region;

a plurality of gate patterns spaced apart from each other in the first direction, the plurality of gate patterns extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the plurality of gate patterns not being in the active cutting region; and

a conductive isolated gate contact region in contact with the plurality of gate patterns outside of the active region, the conductive isolated gate contact region electrically connecting two gate patterns of the plurality of gate patterns to each other.

2. The integrated circuit device as claimed in claim 1 , wherein the active cutting region includes a first active cutting region and a second active cutting region respectively located on opposite sides of the active region in the first direction.

3. The integrated circuit device as claimed in claim 2 , wherein the conductive isolated gate contact region includes a first conductive isolated gate contact region and a second conductive isolated gate contact region respectively located on opposite sides of the active region in the second direction.

4. The integrated circuit device as claimed in claim 1 , wherein the plurality of gate patterns intersects with the active region and the fin active pattern over the active region and the fin active pattern and extends to the outside of the active region.

5. The integrated circuit device as claimed in claim 1 , wherein the conductive isolated gate contact region includes a first conductive isolated gate contact region and a second conductive isolated gate contact region respectively located on opposite sides of the active region in the second direction.

6. The integrated circuit device as claimed in claim 1 , wherein the fin active pattern includes a plurality of fin active patterns spaced apart from each other in the second direction.

7. The integrated circuit device as claimed in claim 1 , further comprising a first combined gate cutting region and a second combined gate cutting region respectively located at opposite sides of the plurality of gate patterns in the second direction.

8. The integrated circuit device as claimed in claim 1 , further comprising gate cutting regions spaced apart from the plurality of gate patterns on opposite sides of the conductive isolated gate contact region in the first direction.

9. An integrated circuit device, comprising:

an active region;

a fin active pattern extending on the active region in a first direction, the fin active pattern including a source region and a drain region;

a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction;

a gate cutting region located around the active region and the fin active pattern such that the gate cutting region is spaced apart from the gate pattern on one side of the gate pattern in the first direction; and

an insulating first combined gate cutting region and an insulating second combined gate cutting region respectively located on opposite sides of the gate pattern in the second direction.

10. The integrated circuit device as claimed in claim 9 , wherein the gate cutting region is spaced apart from the gate pattern on opposite sides of the gate pattern in the first direction.

11. The integrated circuit device as claimed in claim 10 , wherein the gate cutting region includes:

a first gate cutting region and a second gate cutting region at one side of the active region and the fin active pattern, the first gate cutting region and the second gate cutting region being spaced apart from the gate pattern on opposite sides of the gate pattern in the first direction; and

a third gate cutting region and a fourth gate cutting region at another side of the active region and the fin active pattern, the third gate cutting region and the fourth gate cutting region being respectively symmetrical to the first gate cutting region and the second gate cutting region in the second direction.

12. The integrated circuit device as claimed in claim 10 , wherein:

the fin active pattern includes a plurality of fin active patterns spaced apart from each other in the second direction, and

the gate pattern includes a plurality of gate patterns spaced apart from each other in the first direction.

13. The integrated circuit device as claimed in claim 10 , further comprising a first active cutting region and a second active cutting region on opposite sides of the active region in the first direction.

14. The integrated circuit device as claimed in claim 10 , further comprising isolated gate contact regions in contact with the gate pattern outside the active region, the isolated gate contact regions being respectively on opposite sides of the active region in the second direction.

15. An integrated circuit device, comprising a plurality of unit metal-oxide semiconductor (MOS) transistors arranged in an array form apart from each other in a first direction and a second direction perpendicular to the first direction,

wherein each of the unit MOS transistors includes:

an active region;

a plurality of fin active patterns extending on the active region in the first direction and spaced apart from each other in the second direction, each fin active pattern including a source region and a drain region;

active cutting regions on opposite sides of the active region in the first direction;

a plurality of gate patterns extending across the active region and the plurality of fin active patterns in the second direction, the plurality of gate patterns being spaced apart from each other in the first direction;

gate cutting regions around the active region and the plurality of fin active patterns, the gate cutting regions being spaced apart from the plurality of gate patterns on opposite sides of the plurality of gate patterns in the first direction; and

conductive isolated gate contact regions in contact with the plurality of gate patterns outside the active region, the conductive isolated gate contact regions being on opposite sides of the active region in the second direction and electrically connecting two gate patterns of the plurality of gate patterns to each other.

16. The integrated circuit device as claimed in claim 15 , wherein the gate cutting regions include:

a first gate cutting region and a second gate cutting region spaced apart from the plurality of gate patterns on opposite sides of the plurality of gate patterns in the first direction; and

a third gate cutting region and a fourth gate cutting region respectively located symmetrically to the first gate cutting region and the second gate cutting region with respect to the active region in the second direction.

17. The integrated circuit device as claimed in claim 15 , wherein each of the active cutting regions and the gate cutting regions is a region in which the plurality of gate patterns are not formed.

18. The integrated circuit device as claimed in claim 15 , wherein:

the plurality of fin active patterns include a first fin active pattern and a second fin active pattern,

the plurality of gate patterns include a first gate pattern and a second gate pattern, and

each of the conductive isolated gate contact regions is a region in contact with both the first gate pattern and the second gate pattern.