Semiconductor device
A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.
1. A device, comprising:
a substrate having a semiconductor fin;
a first dielectric layer disposed on and in contact with a portion of the semiconductor fin;
a second dielectric layer disposed on and in contact with another portion of the semiconductor fin, wherein an area of the first dielectric layer in contact with the portion of the semiconductor fin is greater than an area of the second dielectric layer in contact with the another portion of the semiconductor fin, and a thickness of the first dielectric layer is different than a thickness of the second dielectric layer;
a first gate disposed on the first dielectric layer and across the semiconductor fin, and in contact with an upper surface of the first dielectric layer;
a second gate disposed on the second dielectric layer and across the semiconductor fin, wherein the first dielectric layer is in contact with side surfaces of the second gate, and a width of the second gate is greater than a width of the first gate.
2. The device according to claim 1 , further comprising a plurality of insulators disposed on the substrate and sandwiched in between the first dielectric layer and the substrate.
3. The device according to claim 1 , further comprising a pair of first spacers and a pair of second spacers disposed on and in contact with the first dielectric layer, wherein the pair of first spacers are located on two sides of the first gate, the pair of second spacers are located on two sides of the second gate.
4. The device according to claim 3 , wherein the second dielectric layer is sandwiched in between the pair of second spacers and in contact with the pair of second spacers.
5. The device according to claim 1 , wherein the thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and the thickness of the second dielectric layer ranges from 5 nm to 50 nm.
6. The device according to claim 1 , wherein a height of the first gate is different than a height of the second gate.
7. The device according to claim 1 , further comprising interlayer dielectric layers disposed on and in contact with the first dielectric layer.
8. A device, comprising:
a substrate comprising trenches and semiconductor fins between trenches;
a plurality of insulators located in the trenches, wherein the plurality of insulators comprises a first portion with a planar top surface and a second portion that is recessed from the planar top surface of the first portion;
a first dielectric layer disposed on the semiconductor fins and covering up the planar top surface of the first portion of the plurality of insulators;
a second dielectric layer disposed on the semiconductor fins and over the second portion of the plurality of insulators, wherein the second portion of the plurality of insulators is partially exposed by the second dielectric layer, and a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer;
a first gate disposed on the first dielectric layer and across the semiconductor fins, and located over the first portion of the plurality of insulators;
a second gate disposed on the second dielectric layer across the semiconductor fins, wherein the second gate covers up the second portion of the plurality of insulators.
9. The device according to claim 8 , further comprising a pair of first spacers and a pair of second spacers disposed on and in contact with the first dielectric layer, wherein the pair of first spacers are located on two sides of the first gate, the pair of second spacers are located on two sides of the second gate.
10. The device according to claim 9 , wherein a distance between the pair of second spacers is greater than a distance between the pair of first spacers.
11. The device according to claim 9 , wherein the second dielectric layer is located in between the pair of second spacers and in contact with the pair of second spacers.
12. The device according to claim 8 , wherein the thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and the thickness of the second dielectric layer ranges from 5 nm to 50 nm.
13. The device according to claim 8 , wherein a width and a height of the first gate is different than a width and a height of the second gate.
14. The device according to claim 8 , further comprising interlayer dielectric layers disposed over the first portion of the plurality of insulators.
15. A device, comprising:
a substrate having a semiconductor fin;
a first gate disposed on the substrate across the semiconductor fin;
a second gate disposed on the substrate across the semiconductor fin, wherein a width and a height of the first gate is different than a width and a height of the second gate;
interlayer dielectric layers located on the substrate over the semiconductor fin and surrounding the first gate and the second gate, wherein a top surface of the interlayer dielectric layers is coplanar with top surfaces of the first gate and the second gate;
a first dielectric layer located below the first gate and the interlayer dielectric layers, and in contact with the first gate and the interlayer dielectric layers, wherein the first dielectric layer is in contact with side surfaces of the second gate;
a second dielectric layer located below the second gate and in contact with the semiconductor fin, wherein the second dielectric layer is confined in an area overlapped with the second gate, and a thickness of the second dielectric layer is different than a thickness of the first dielectric layer, and wherein a bottom surface of the second dielectric layer is located at a level below a bottom surface of the first dielectric layer; and
a plurality of insulators disposed on the substrate and located below and in contact with the first dielectric layer, the second dielectric layer and the second gate,
wherein the plurality of insulators is in contact with a first portion of a bottom surface of the second gate, and the second dielectric layer is in contact with a second portion of the bottom surface of the second gate.
16. The device according to claim 15 , further comprising a pair of first spacers and a pair of second spacers disposed on and in contact with the first dielectric layer, wherein the pair of first spacers are located on two sides of the first gate, the pair of second spacers are located on two sides of the second gate.
17. The device according to claim 15 , wherein a width of the first gate ranges from 5 nm to 50 nm and a width of the second gate is greater than the first gate.
18. The device according to claim 15 , wherein the second gate protrudes into the plurality of insulators.
19. The device according to claim 15 , wherein side surfaces of the first dielectric layer are in contact with side surfaces of the second dielectric layer.
20. The device according to claim 15 , wherein the plurality of insulators is physically separated from the first gate by the first dielectric layer.