Semiconductor devices and methods
Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.
1. A method comprising:
depositing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially over a semiconductor substrate;
etching the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the semiconductor substrate to form a fin, wherein a top surface of the fin has a L-shape in a top-down view;
etching the first semiconductor layer and the third semiconductor layer to form a first nanostructure from the second semiconductor layer;
forming a gate dielectric layer around the first nanostructure; and
forming a gate electrode around the gate dielectric layer.
2. The method of claim 1 , wherein in the top-down view the fin has a first width and a second width, wherein the first width is measured along a direction that is parallel to a direction in which the second width is measured, and wherein a difference between the first width and the second width is in a range from 2 nm and 16 nm.
3. The method of claim 2 , wherein a ratio between the first width and the second width is in a range from 4:1 to 15:1.
4. The method of claim 2 , further comprising:
forming a first source/drain region adjacent to a first side of an active region of the fin, the first side of the fin corresponding to the first width; and
forming a second source/drain region adjacent to a second side of the active region of the fin, the second side of the fin corresponding to the second width.
5. The method of claim 4 , wherein a third width of the first source/drain region and a fourth width of the second source/drain region are different, wherein the third width and the fourth width are measured in parallel directions.
6. The method of claim 4 , wherein forming the gate electrode comprises forming the gate electrode to partially overlap a first corner of the first nanostructure, the first corner of the first nano structure being adjacent to a portion of the fin with the first width.
7. The method of claim 4 , wherein forming the gate electrode comprises forming the gate electrode to partially overlap a second corner of the first nanostructure, the second corner of the first nanostructure being adjacent to a portion of the fin with the second width.
8. A method comprising:
depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of first layers that alternate with a plurality of second layers, wherein a material of the plurality of first layers is different from a material of the plurality of second layers;
patterning the multi-layer stack to form a fin, wherein in a top-down view the fin comprises:
an active region;
a first portion of the fin adjacent to a first end of the active region; and
a second portion of the fin adjacent to a second end of the active region, wherein the active region is disposed between the first portion of the fin and the second portion of the fin, the first end of the active region having a first width, and the second end of the active region having a second width different from the first width;
removing the plurality of first layers to form a plurality of nanostructures from the plurality of second layers; and
depositing a gate electrode around each of the plurality of nano structures.
9. The method of claim 8 further comprising:
forming a first source/drain region adjacent to the first end of the active region; and
forming a second source/drain region adjacent to the second end of the active region, the first source/drain region having a third width that is different than a fourth width of the second source/drain region, wherein the third width is measured in a direction that is parallel to a direction in which the fourth width is measured.
10. The method of claim 8 , wherein a difference between the first width and the second width is in a range from 2 nm and 16 nm.
11. The method of claim 8 , wherein a first nanostructure of the plurality of nanostructures comprises a first corner at the first end of the active region, the first corner being located at least partially beneath the gate electrode, wherein the first width is larger than the second width.
12. The method of claim 11 , wherein the first nanostructure comprises a second corner at the second end of the active region, the second corner being located at least partially beneath a first gate spacer.
13. The method of claim 8 , wherein a second nanostructure of the plurality of nanostructures comprises a third corner at the first end of the active region, the third corner being located at least partially beneath a second gate spacer, wherein the first width is larger than the second width.
14. The method of claim 13 , wherein the second nanostructure comprises a fourth corner at the second end of the active region, the fourth corner being located at least partially beneath the gate electrode.
15. A device comprising:
a plurality of channel regions over a substrate;
a gate dielectric surrounding each of the plurality of channel regions, wherein the plurality of channel regions is vertically stacked;
a gate electrode around the gate dielectric;
a first source/drain region on a first side of the gate electrode; and
a second source/drain region on a second side of the gate electrode, wherein a first channel width of each of the plurality of channel regions on the first side is larger than a second channel width of each of the plurality of channel regions on the second side, wherein the first channel width and the second channel width are measured along directions parallel to each other.
16. The device of claim 15 , wherein a ratio between the first channel width and the second channel width is in a range from 4:1 to 15:1.
17. The device of claim 15 , wherein the first source/drain region comprises a third width that is larger than a fourth width of the second source/drain region, wherein the third width and the fourth width are measured in directions parallel to directions in which the first channel width and the second channel width are measured.
18. The device of claim 15 , wherein a difference between the first channel width and the second channel width is in a range from 2 nm and 16 nm.
19. The device of claim 15 further comprising:
a first gate spacer disposed adjacent to the first side of the gate electrode; and
a second gate spacer disposed adjacent the second side of the gate electrode, wherein a thickness of a portion of each of the plurality of channel regions between the first gate spacer and the second gate spacer changes in a direction from the first gate spacer towards the second gate spacer.
20. The device of claim 15 , wherein the first channel width and the second channel width are in a range from 8 nm and 50 nm.