Semiconductor device and method of forming the same
A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.
1. A semiconductor device comprising:
a lower structure;
a stacked structure on the lower structure and including a first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer and a cell gate pattern between the first and second interlayer insulating layers;
a separation structure penetrating through the stacked structure; and
a memory vertical structure penetrating through the stacked structure,
wherein the memory vertical structure includes a first portion located on a same level as a level of the cell gate pattern and second portions located on a same level as a level of the first and second interlayer insulating layers,
wherein each of the second portions has a width smaller than a width of the first portion,
wherein the memory vertical structure includes a first dielectric layer and a second dielectric layer, in contact with each other in the second portions, extended toward the first portion, and spaced apart from each other in the first portion,
wherein the memory vertical structure further includes a data storage pattern disposed between the first dielectric layer and the second dielectric layer in the first portion,
wherein the first dielectric layer contacts the cell gate pattern and the first and second insulating layers,
wherein the cell gate pattern includes an upper surface contacting the second insulating layer, a lower surface contacting the first insulating layer and a first side contacting the first dielectric layer and a second side contacting the separation structure, and
wherein the first side of the cell gate pattern includes:
a central protruding portion protruding in a direction toward the first portion of the memory vertical structure in the cell gate pattern;
a first edge protruding portion adjacent to the first interlayer insulating layer;
a second edge protruding portion adjacent to the second interlayer insulating layer;
a first recess portion between the central protruding portion and the first edge protruding portion; and
a second recess portion between the central protruding portion and the first edge protruding portion.
2. The semiconductor device of claim 1 , wherein the first dielectric layer covers a first side surface of the data storage pattern, opposing the cell gate pattern, an upper surface of the data storage pattern, and a lower surface of the data storage pattern, and
wherein the second dielectric layer covers a second side surface of the data storage pattern opposing the first side surface of the data storage pattern.
3. The semiconductor device of claim 2 , wherein the memory vertical structure further includes a channel layer and an insulating core pattern,
wherein the channel layer is on a side surface of the insulating core pattern,
wherein the first dielectric layer, the data storage pattern, the second dielectric layer are between the channel layer and the stacked structure.
4. The semiconductor device of claim 1 , wherein the cell gate pattern includes a cell gate electrode and a cell gate insulating layer, and
wherein the cell gate insulating layer is disposed between the first insulating layer and a lower surface of the cell gate electrode, the second insulating layer and an upper surface of the cell gate electrode, and the first dielectric layer and a first side surface of the cell gate electrode.
5. The semiconductor device of claim 4 , wherein the cell gate insulating layer is formed of a high-k dielectric material having a dielectric constant higher than a dielectric constant of the first dielectric layer.
6. The semiconductor device of claim 1 , wherein a distance between the upper surface of the cell gate pattern and the lower surface of the cell gate pattern is greater than a distance between an upper surface of the data storage pattern and a lower surface of the data storage pattern.
7. The semiconductor device of claim 1 , wherein the data storage pattern includes an overlapping portion overlapping the first and second interlayer insulating layers in a vertical direction and a non-overlapping portion not overlapping the first and second interlayer insulating layers in the vertical direction, and
wherein the vertical direction is perpendicular to an upper surface of the lower structure.
8. The semiconductor device of claim 7 , wherein a width of the overlapping portion of the data storage pattern in a horizontal direction is different from a width of the non-overlapping portion in the horizontal direction, and
wherein the horizontal direction is a direction parallel to an upper surface of the lower structure.
9. The semiconductor device of claim 7 , wherein a width of the overlapping portion of the data storage pattern in a horizontal direction is greater than a width of the non-overlapping portion in the horizontal direction, and
wherein the horizontal direction is a direction parallel to an upper surface of the lower structure.
10. The semiconductor device of claim 1 , wherein the lower structure includes a first substrate, a second substrate on the first substrate, and a peripheral circuit region including a peripheral transistor and between the first substrate and the second substrate,
wherein the stacked structure is on the second substrate,
wherein the second substrate includes a polysilicon layer, and
wherein the memory vertical structure contacts the polysilicon layer.