Laterally diffused MOSFET and method of fabricating the same
View Patent ↗A semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type, a source region and a body contact region in the second semiconductor region. The semiconductor device also includes a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region, a gate dielectric layer overlying both the channel region and a portion of the first semiconductor region, and a gate electrode overlying the gate dielectric layer. The semiconductor device further includes a conformal conductive layer covering an upper surface of the body contact region and a side surface of the source region.
1. A semiconductor device comprising:
a first semiconductor region having a first conductivity type;
a second semiconductor region having a second conductivity type;
a source region having the first conductivity type in the second semiconductor region;
a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region;
a gate dielectric layer overlying both the channel region and a portion of the first semiconductor region;
a gate electrode overlying the gate dielectric layer;
a body contact region in the second semiconductor region;
a spacer, overlying the source region, having a first side laterally adjacent to the gate electrode, wherein the first side of the spacer is vertically aligned with a first side surface of the source region, and wherein the first side surface is an interface that separates the source region having the first conductivity type from the second semiconductor region having the second conductivity type; and
a conformal conductive layer covering an upper surface of the body contact region and a second side surface of the source region.
2. The semiconductor device of claim 1 , further comprising:
a contact plug connecting to the conformal conductive layer through a dielectric isolation layer.
3. The semiconductor device of claim 1 , wherein the conformal conductive layer is a layer of metal silicide.
4. The semiconductor device of claim 1 , further comprising:
a drain region in the first semiconductor region.
5. The semiconductor device of claim 4 , further comprising:
an isolation region, in the first semiconductor region, located laterally between the drain region and the second semiconductor region.
6. The semiconductor device of claim 1 , wherein the spacer has a second side vertically aligned with the second side surface of the source region.
7. The semiconductor device of claim 1 , wherein the body contact region has a first side vertically aligned with the second side surface of the source region.
8. The semiconductor device of claim 7 , wherein the upper surface of the body contact region is recessed from a top surface of the source region with a depth that is less than a distance between the top surface of the source region and a bottom surface of the source region.
9. The semiconductor device of claim 1 , wherein the source region overlies the body contact region.
10. The semiconductor device of claim 9 , wherein the upper surface of the body contact region is recessed from a top surface of the source region with a depth that is larger than or equal to a distance between the top surface of the source region and a bottom surface of the source region.
11. The semiconductor device of claim 9 , wherein the body contact region has a first side vertically aligned with a side of the gate electrode.
12. A semiconductor device comprising:
a first semiconductor region having a first conductivity type;
a second semiconductor region having a second conductivity type;
a source region having the first conductivity type in the second semiconductor region;
a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region;
a gate dielectric layer overlying both the channel region and a portion of the first semiconductor region;
a gate electrode overlying the gate dielectric layer;
a body contact region in the second semiconductor region; and
a spacer, overlying the source region, having a first side laterally in direct contact with the gate electrode and vertically aligned with a first side surface of the source region, wherein the first side surface is an interface that separates the source region having the first conductivity type from the second semiconductor region having the second conductivity type, and wherein the spacer has a second side vertically aligned with a second side surface of the source region.
13. The semiconductor device of claim 12 , further comprising:
a drain region in the first semiconductor region; and
an isolation region, in the first semiconductor region, located laterally between the drain region and the second semiconductor region.
14. The semiconductor device of claim 13 , further comprising:
a conformal conductive layer covering an upper surface of the body contact region and the second side surface of the source region.
15. The semiconductor device of claim 12 , wherein the body contact region is in direct contact with the source region.
16. A semiconductor device comprising:
a first semiconductor region having a first conductivity type;
a second semiconductor region having a second conductivity type;
a source region having the first conductivity type in the second semiconductor region;
a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region;
a drain region in the first semiconductor region;
an isolation region in the first semiconductor region and located laterally between the drain region and the second semiconductor region;
a gate electrode atop of both the channel region and a portion of the first semiconductor region;
a body contact region in the second semiconductor region; and
a spacer, overlying the source region, having a first side laterally in direct contact with the gate electrode and vertically aligned with a first side surface of the source region, wherein the first side surface is an interface that separates the source region having the first conductivity type from the second semiconductor region having the second conductivity type and wherein the spacer has a second side vertically aligned with a second side surface of the source region.
17. The semiconductor device of claim 16 , wherein the isolation region is a shallow trench isolation in the first semiconductor region.
18. The semiconductor device of claim 16 , wherein the isolation region is a local oxidation of silicon region in the first semiconductor region.
19. The semiconductor device of claim 16 , wherein the body contact region is in direct contact with the source region.
20. The semiconductor device of claim 19 , further comprising:
a conformal conductive layer covering an upper surface of the body contact region and the second side surface of the source region.