Methods of forming microelectronic devices, and related microelectronic devices, memory devices, electronic systems, and additional methods
A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.
1. A microelectronic device, comprising:
conductive bit lines extending in a first horizontal direction;
insulative line structures vertically adjacent the conductive bit lines and extending in the first horizontal direction;
partially filled trenches intervening between the conductive bit lines in a second horizontal direction orthogonal to the first horizontal direction, the partially filled trenches comprising:
an isolation material on side surfaces of the conductive bit lines and the insulative line structures; and
air gaps surrounded by the isolation material and vertically overlapping the conductive bit lines;
conductive contact structures vertically extending through portions of the insulative line structures and directly physically contacting the conductive bit lines, the conductive contact structures partially vertically overlapping the air gaps; and
conductive pad structures vertically adjacent the conductive contact structures;
wherein vertically lower portions of the conductive contact structures are relatively horizontally narrower than vertically upper portions of the conductive contact structures; and
further comprising dielectric spacer structures physically contacting side surfaces of the vertically upper portions of the conductive contact structures, but not physically contacting side surfaces of the vertically lower portions of the conductive contact structures.
2. The microelectronic device of claim 1 , wherein the isolation material horizontally extends over upper surfaces of the insulative line structures.
3. The microelectronic device of claim 1 , wherein the conductive pad structures comprise copper.
4. A memory device, comprising:
a memory array region comprising:
a stack structure comprising multiple tiers vertically adjacent one another, each tier of the multiple tiers comprising a conductive structure and an insulating structure vertically adjacent the conductive structure;
strings of memory cells each vertically extending through the multiple tiers of the stack structure;
a source structure vertically overlying the stack structure and coupled to the strings of memory cells;
conductive digit lines vertically underlying the stack structure and coupled to the strings of memory cells;
dielectric cap structures directly vertically underlying the conductive digit lines;
an isolation material horizontally interposed between the conductive digit lines and horizontally interposed between the dielectric cap structures; and
air gaps surrounded by the isolation material, the air gaps vertically overlapping and horizontally alternating with the conductive digit lines;
a control logic region vertically underlying the memory array region and comprising control logic devices configured to effectuate a portion of control operations for the strings of memory cells; and
an interconnect region vertically interposed between the memory array region and the control logic region and comprising structures coupling the conductive digit lines of the memory array region to the control logic devices of the control logic region, the structures comprising conductive contact structures vertically extending through the dielectric cap structures of the memory array region and directly physically contacting the conductive digit lines, the conductive contact structures partially vertically overlapping the air gaps;
wherein the structures of the interconnect region further comprise:
additional conductive contact structures physically contacting conductive routing structures within the control logic region; and
conductive pad structures vertically extending from and between the conductive contact structures and the additional conductive contact structures.
5. The memory device of claim 4 , wherein conductive contact structures comprise:
first portions relatively vertically closer to the conductive digit lines; and
second portions relatively vertically closer to the conductive pad structures, the second portions of the conductive contact structures relatively horizontally wider than the first portions of the conductive contact structures.
6. The memory device of claim 5 , further comprising dielectric spacer structures horizontally interposed between the second portions of the conductive contact structures and each of the isolation material and the dielectric cap structures.