Multiplexing control information in a physical uplink data channel
For multiplexing control information in a physical uplink data channel, a user equipment (UE) includes receiving a configuration for a first set of values and receiving a downlink control information (DCI) format scheduling a transmission of a physical uplink shared data channel (PUSCH) over a set of resource elements (REs) and including a field providing an index. The method further includes determining a first value from the first set of values based on the index, determining a first subset of REs from the set of REs, for multiplexing first uplink control information (UCI), based on the first value, and transmitting the first UCI in the PUSCH.
1. A method, comprising:
determining that a first number of control information bits is smaller than a predetermined number of bits;
appending a second number of bits, each having a zero value, to the first number of control information bits, wherein the second number of bits is equal to a difference between the first number of control information bits and the predetermined number of bits;
computing first cyclic redundancy check (CRC) bits for the first number of control information bits and the second number of bits; and
encoding the first number of control information bits, the second number of bits, and the first CRC bits using a polar code.
2. The method of claim 1 , wherein:
the predetermined number of bits is a minimum number of bits for encoding using a polar code; and
the predetermined number of bits is twelve.
3. The method of claim 1 , further comprising:
determining that a second number of control information bits is larger than or equal to the predetermined number of bits;
computing second CRC bits for the second number of control information bits; and
encoding the second number of control information bits and the second CRC bits using a polar code.
4. The method of claim 3 , wherein a number of the first CRC bits is same as a number of the second CRC bits.
5. The method of claim 1 , wherein:
a number of bits for a first CRC check is zero when the first number of control information bits is smaller than a minimum number of control information bits.
6. The method of claim 1 , wherein a number of the first CRC bits depends on the first number of control information bits.
7. An apparatus, comprising:
a processor configured to:
determine that a first number of control information bits is smaller than a predetermined number of bits;
append a second number of bits, each having a zero value, to the first number of control information bits, wherein the second number of bits is equal to a difference between the first number of control information bits and the predetermined number of bits;
compute first cyclic redundancy check (CRC) bits for the first number of control information bits and the second number of bits; and
an encoder operably connected to the processor, the encoder configured to encode the first number of control information bits, the second number of bits, and the first CRC bits using a polar code.
8. The apparatus of claim 7 , wherein:
the predetermined number of bits is a minimum number of bits for encoding using a polar code; and
the predetermined number of bits is twelve.
9. The apparatus of claim 7 , wherein:
the processor is further configured to:
determine that a second number of control information bits is larger than or equal to the predetermined number of bits, and
compute second CRC bits for the second number of control information bits; and
the encoder is further configured to encode the second number of control information bits and the second CRC bits using a polar code.
10. The apparatus of claim 9 , wherein a number of the first CRC bits is same as a number of the second CRC bits.
11. The apparatus of claim 7 , wherein:
a number of bits for a first CRC check is zero when the first number of control information bits is smaller than a minimum number of control information bits.
12. The apparatus of claim 7 , wherein a number of the first CRC bits depends on the first number of control information bits.
13. An apparatus, comprising:
a decoder configured to decode, using a polar code, a first codeword comprising a predetermined number of bits and first CRC bits, wherein:
the predetermined number of bits includes a first number of control information bits followed by a second number of bits, wherein the second number of bits is equal to a difference between the first number of control information bits and the predetermined number of bits, and
the first number of control information bits is smaller than the predetermined number of bits; and
a processor operably connected to the decoder, the decoder configured to:
compute a first CRC check based on the first CRC bits, and
process the first number of control information bits when the first CRC check is positive.
14. The apparatus of claim 13 , wherein:
the processor is further configured to process the first number of control information bits when each bit from the second number of bits has value zero.
15. The apparatus of claim 13 , wherein:
the predetermined number of bits is a minimum number of bits for encoding using a polar code; and
the predetermined number of bits is twelve.
16. The apparatus of claim 13 , wherein:
the decoder is further configured to decode, using a polar code, a second codeword comprising a second number of control information bits and second CRC bits; and
the processor is further configured to:
determine that the second number of control information bits is larger than or equal to the predetermined number of bits,
compute a second CRC check based on the second CRC bits, and
process the second number of control information bits when the second CRC check is positive.
17. The apparatus of claim 16 , wherein a number of the first CRC bits is same as a number of the second CRC bits.
18. The apparatus of claim 13 , wherein:
a number of first CRC bits is zero when the first number of control information bits is smaller than a minimum number of control information bits.
19. The apparatus of claim 13 , wherein a number of the first CRC bits depends on the first number of control information bits.