Nonvolatile memory device
A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.
1. A nonvolatile memory device comprising:
a substrate including a cell array region;
a first gate electrode including an opening on the cell array region of the substrate;
a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate; and
a word line cutting region cutting the opening and the convex portions.
2. The nonvolatile memory device of claim 1 , wherein the convex portions are located above the opening.
3. The nonvolatile memory device of claim 2 , further comprising:
a channel structure passing through the first gate electrode and the plurality of second gate electrodes,
wherein the channel structure is not disposed on the convex portions.
4. The nonvolatile memory device of claim 1 , wherein the first gate electrode and the plurality of second gate electrodes extend in a first direction, and
as a distance between the substrate and each of the plurality of second gate electrodes decreases, a width in the first direction of the respective convex portion of each of the plurality of second gate electrodes increases.
5. The nonvolatile memory device of claim 1 , wherein the first gate electrode and the plurality of second gate electrodes extend in a first direction,
the opening has a first width in the first direction,
the convex portion included in one of the plurality of second gate electrodes, which is adjacent to the first gate electrode, has a second width in the first direction, and
the first width is smaller than the second width.
6. The nonvolatile memory device of claim 5 , wherein the word line cutting region has a third width in the first direction, and
the third width is smaller than the first width and the second width.
7. The nonvolatile memory device of claim 1 , wherein the first gate electrode and the plurality of second gate electrodes extend in a first direction,
the opening has a first width in the first direction,
a first subset of the plurality of second gate electrodes has a width larger than the first width in the first direction, and
a second subset of the plurality of second gate electrodes has a width smaller than the first width in the first direction.
8. The nonvolatile memory device of claim 1 , further comprising:
a first insulating film disposed between and in contact with the first gate electrode and one of the plurality of second gate electrodes,
wherein the first insulating film includes tetraethyl orthosilicate (TEOS).
9. The nonvolatile memory device of claim 8 , wherein the first insulating film includes:
a first interlayer insulating film formed along profiles of the first gate electrode and the opening; and
a second interlayer insulating film formed between the first interlayer insulating film and the one of the plurality of second gate electrodes.
10. The nonvolatile memory device of claim 8 , further comprising:
a second insulating film covering the plurality of second gate electrodes,
wherein the second insulating film includes the same material as the first insulating film.
11. The nonvolatile memory device of claim 8 , further comprising:
a second insulating film disposed above the one of the plurality of second gate electrodes and disposed on and in contact with another one of the plurality of second gate electrodes,
wherein a top surface of the second insulating film is flat.
12. The nonvolatile memory device of claim 11 , wherein the second insulating film includes the same material as the first insulating film.
13. A nonvolatile memory device comprising:
a plurality of gate electrodes extending in a first direction on a substrate and stacked in a second direction perpendicular to the first direction;
a first channel structure passing through the plurality of gate electrodes; and
a second channel structure passing through the plurality of gate electrodes and spaced apart from the first channel structure by a first length in the first direction,
wherein at least a subset of the plurality of gate electrodes each includes a convex portion having an outward curve extending toward the substrate and having a second length in the first direction,
the convex portion is formed between the first channel structure and the second channel structure, and
the first length is greater than the second length.
14. The nonvolatile memory device of claim 13 , wherein the plurality of gate electrodes include:
a first gate electrode including a portion separated by a third length in the first direction between the first channel structure and the second channel structure above the substrate; and
a second gate electrode including the convex portion,
wherein the convex portion is formed above the center of the separated portion of the first gate electrode, and
the third length is smaller than the first length.
15. The nonvolatile memory device of claim 13 , wherein as a distance between the substrate and each of the gate electrodes within the subset of the plurality of gate electrodes including the convex portion decreases, a width in the first direction of the respective convex portions increases.
16. The nonvolatile memory device of claim 14 , wherein the first gate electrode is a ground select line.
17. The nonvolatile memory device of claim 13 , further comprising:
a word line cutting region cutting the subset of the plurality of gate electrodes on the convex portions.
18. A nonvolatile memory device comprising:
a substrate including a cell array region and an extension region;
a first gate electrode including a first opening above the cell array region on the substrate and a second opening above the extension region on the substrate;
a plurality of second gate electrodes stacked on the first gate electrode and each including a first convex portion corresponding to the first opening and having an outward curve extending toward the substrate and a second convex portion corresponding to the second opening and having an outward curve extending toward the substrate;
a channel structure passing through the first gate electrode and the plurality of second gate electrodes on the cell array region; and
a word line cutting region cutting the first opening and the first convex portions,
wherein as a distance between the substrate and the first convex portions and the second convex portions decreases, a width of the first convex portions and the second convex portions increases.
19. The nonvolatile memory device of claim 18 , wherein the channel structure is not formed on the first convex portions.
20. The nonvolatile memory device of claim 18 , further comprising:
a first interlayer insulating film formed on the first gate electrode along profiles of the first gate electrode and the first and second openings and having an upper surface, at least a portion of which has an angled shape; and
a second interlayer insulating film formed between the first interlayer insulating film and the plurality of second gate electrodes and having an upper surface with a convex portion having an outward curve extending toward the substrate,
wherein the first interlayer insulating film and the second interlayer insulating film include the same material.