Methods of hardware and software-coordinated opt-in to advanced features on hetero ISA platforms

1. A processor, comprising:

a plurality of processing elements associated with heterogeneous instruction set architectures, wherein the plurality of processing elements comprises at least a first processing element associated with a first instruction set architecture and a second processing element associated with a different instruction set architecture;

wherein the processor is configured to:

receive, while operating in a user mode of operation and via an application programming interface (API), a request from an application executed by the first processing element of the plurality of processing elements to enable a feature associated with an instruction set architecture of the heterogeneous instruction set architectures;

based on the first processing element supporting the feature and an operating system permitting the application to utilize the feature, enabling while remaining operating in the user mode of operation, the application to utilize the feature provided by the first processing element; and

based on the first processing element not supporting the feature or the operating system not permitting the application to utilize the feature, enter a kernel mode of operation to determine whether the second processing element can provide the feature.

2. The processor of claim 1 , wherein the processor comprises a kernel mode register comprising a plurality of values indicative of a plurality of features the operating system will permit the application to utilize, wherein the plurality of features comprises the feature.

3. The processor of claim 2 , wherein the processor is configured to determine whether the operating system will permit the application to utilize the feature based on the plurality of values.

4. The processor of claim 1 , wherein, after entering the kernel mode of operation, the processor is configured to enable the application to utilize the feature by:

determining the second processing element of the processor can provide the feature;

causing a software thread associated with the request to be addressed by the second processing element; and

causing the second processing element to provide the feature.

5. The processor of claim 1 , wherein the processor is configured to:

begin processing a first software thread associating with the application using the first processing element after the application has been enabled to use the feature;

context switch out the first software thread in order to process a second software thread;

process the second software thread using the first processing element;

determine whether the first processing element is configured to enable the application to utilize the feature when resuming the first software thread; and

resume processing the first software thread.

6. The processor of claim 5 , wherein the processor is configured to resume processing the first software thread by:

utilizing the first processing element upon determining that the first processing element is configured to enable the application to utilize the feature; and

utilizing the second processing element of the processor upon determining that the first processing element is not configured to enable the application to utilize the feature.

7. The processor of claim 1 , wherein:

the processor comprises a microprocessor; and

the plurality of processing elements comprise a plurality of cores of the microprocessor.

8. A processor-implemented method implemented in a processor having a plurality of processing elements associated with heterogeneous instruction set architectures, wherein the plurality of processing elements comprises at least a first processing element associated with a first instruction set architecture and a second processing element associated with a different instruction set architecture, the processor- implemented method, comprising:

receiving by the processor, while operating in a user mode of operation and via an application programming interface (API), a request from an application executed by the first processing element of the plurality of processing elements to enable a feature associated with an instruction set architecture of the heterogeneous instruction set architectures;

based on the first processing element supporting the feature and an operating system permitting the application to utilize the feature, enabling while remaining operating in the user mode of operation, the application to utilize the feature provided by the first processing element; and

based on the first processing element not supporting the feature or the operating system not permitting the application to utilize the feature, entering a kernel mode of operation to determine whether the second processing element can provide the feature.

9. The processor-implemented method of claim 8 , wherein enabling the application to utilize the feature comprises causing, by the processor while operating in the user mode of operation, a bit of a register associated with the feature to be modified.

10. The processor-implemented method of claim 9 , comprising:

determining, by the application programming interface, whether the bit has been modified; and

providing an indication to the application that sent the request that the application may utilize the feature.

11. The processor-implemented method of claim 10 , comprising determining whether the bit has been modified by determining whether one or more bits of a second register are indicative of the bit having been modified.

12. The processor-implemented method of claim 9 , comprising determining, while in the user mode of operation, whether an operating system will permit the application to utilize the feature.

13. The processor-implemented method of claim 12 , when the operating system will permit the application to utilize the feature and the processing element supports the feature, enabling the feature to be utilized by the application by causing the bit of the register to be modified.

14. The processor-implemented method of claim 8 , wherein the feature is the instruction set architecture.

15. A non-transitory computer-readable medium comprising instructions that, when executed by a processor having a plurality of processing elements associated with heterogeneous instruction set architectures, wherein the plurality of processing elements comprises at least a first processing element associated with a first instruction set architecture and a second processing element associated with a different instruction set architecture, cause the processor to:

receive, while operating in a user mode of operation and via an application programming interface (API), a request from an application executed by the first processing element of the plurality of processing elements to enable a feature associated with an instruction set architecture of the heterogeneous instruction set architectures;

based on the first processing element supporting the feature and an operating system permitting the application to utilize the feature, enabling while remaining operating in the user mode of operation, the application to utilize the feature provided by the first processing element; and

based on the first processing element not supporting the feature or the operating system not permitting the application to utilize the feature, enter a kernel mode of operation to determine whether the second processing element can provide the feature.

16. The non-transitory computer-readable medium of claim 15 , wherein after entering the kernel mode of operation, the instructions, when executed, cause the processor to:

enable the application to utilize the feature by:

determining the second processing element of the processor can provide the feature;

causing a software thread associated with the request to be addressed by the second processing element; and

causing the second processing element to provide the feature.