Method of forming a stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell

1. A method comprising:

forming a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, wherein the via couples to a first metal layer;

forming a first capacitor including a non-linear polar material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is in a middle of the first capacitor;

forming a second capacitor including a linear dielectric material, wherein the electrode passes through a middle of the second capacitor;

forming a first plate-line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first plate-line is on an outer portion of the first capacitor; and

forming a second plate-line extending along the x-plane or the z-plane, wherein the second plate-line is on an output portion of the second capacitor.

2. The method of claim 1 , wherein forming the first capacitor includes:

forming a first layer coupled to the electrode, wherein the first layer comprises a first metal;

forming a second layer around the first layer, wherein the second layer comprises a first conductive oxide;

forming a third layer comprising the non-linear polar material, wherein the third layer is around the second layer;

forming a fourth layer around the third layer, wherein the fourth layer comprises a second conductive oxide, and wherein the fourth layer is around the third layer; and

forming a fifth layer around the fourth layer, wherein the fifth layer comprises a fifth metal, and wherein the first plate-line is adjacent to part of the fifth layer.

3. The method of claim 2 , wherein:

the first layer has a first circumference;

the second layer has a second circumference;

the third layer has a third circumference;

the fourth layer has a fourth circumference;

the fifth layer has a fifth circumference;

the fifth circumference is larger than the fourth circumference;

the fourth circumference is larger than the third circumference;

the third circumference is larger than the second circumference; and

the second circumference is larger than the first circumference.

4. The method of claim 1 , wherein forming the second capacitor includes:

forming a first layer coupled to the electrode, wherein the first layer comprises metal;

forming a second layer comprising the linear dielectric material, wherein the second layer is around the first layer; and

forming a third layer around the second layer, wherein the third layer comprises metal, wherein the second plate-line is adjacent to part of the third layer.

5. The method of claim 4 , wherein:

the first layer has a first circumference;

the second layer has a second circumference; and

the third layer has a third circumference, wherein the third circumference is larger than the second circumference, and wherein the second circumference is larger than the first circumference.

6. The method of claim 1 , wherein the non-linear polar material includes one of: ferroelectric material, paraelectric material, or non-linear dielectric.

7. The method of claim 6 , wherein the ferroelectric material includes one of:

Bismuth ferrite (BFO) with a first doping material, wherein the first doping material is one of Lanthanum, or elements from lanthanide series of periodic table;

Lead zirconium titanate (PZT), or PZT with a second doping material, wherein the second doping material is one of La, or Nb;

a relaxor ferroelectric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST);

a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;

a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3;

a hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);

Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;

Hafnium oxides as Hf1-x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y;

Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where ‘y’ includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ or ‘y’ is a fraction;

Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or

an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

8. The method of claim 6 , wherein the paraelectric material includes: SrTiO3, Ba(x)Sr(y)TiO3, HfZrO2, Hf—Si—O, La-substituted PbTiO3, or PMN-PT based relaxor ferroelectrics.

9. The method of claim 1 , wherein the first plate-line and the second plate-line are parallel to a word-line or a bit-line.

10. The method of claim 1 , wherein an effective capacitance of the second capacitor is substantially equal to a linear component of a capacitance of the first capacitor.

11. The method of claim 1 comprising applying a second voltage on the second plate-line, wherein the second voltage on the second plate-line is opposite to a first voltage applied to the first capacitor via the first plate-line to compensate for dielectric capacitor dependent charge.

12. The method of claim 1 , wherein the second plate-line has a second voltage complementary to a first voltage on the first plate-line.

13. A method comprising:

fabricating a transistor, the transistor having a source region and a drain region, and a gate;

depositing a first etch stop layer over a region above the transistor;

fabricating a first via through the first etch stop layer, wherein the first via is coupled to the source region;

fabricating a second via through the first etch stop layer, wherein the second via is coupled to the drain region;

depositing a first metal layer over the first via, the first metal layer extending along an x-plane;

depositing a second etch stop layer over the first metal layer;

forming a third via over the first metal layer by etching through the second etch stop layer, the third via in direct connection to the first metal layer, wherein the third via extends along a y-plane, and wherein the y-plane is orthogonal to an x-plane;

forming a first non-planar stack of materials including a non-linear polar material, wherein the first non-planar stack of materials includes an electrode coupled to the third via, wherein the electrode is in a middle of the first non-planar stack of materials;

forming a second non-planar stack of materials including a linear dielectric material, and wherein the electrode passes through a middle of the second non-planar stack of materials;

forming a first plate-line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first plate-line is on a first portion of the first non-planar stack of materials; and

forming a second plate-line extending along the x-plane or the z-plane, wherein the second plate-line is on a second portion of the second non-planar stack of materials.

14. The method of claim 13 , wherein forming the first non-planar stack of materials includes:

forming a first layer coupled to the electrode, wherein the first layer comprises metal;

forming a second layer around the first layer, wherein the second layer comprises a first conductive oxide;

forming a third layer comprising the non-linear polar material, wherein the third layer is around the second layer;

forming a fourth layer around the third layer, wherein the fourth layer comprises a second conductive oxide, and wherein the fourth layer is around the third layer; and

forming a fifth layer around the fourth layer, wherein the fifth layer comprises metal, and wherein the first plate-line is adjacent to part of the fifth layer.

15. The method of claim 14 , wherein:

the first layer has a first circumference;

the second layer has a second circumference;

the third layer has a third circumference;

the fourth layer has a fourth circumference;

the fifth layer has a fifth circumference;

the fifth circumference is larger than the fourth circumference;

the fourth circumference is larger than the third circumference;

the third circumference is larger than the second circumference; and

the second circumference is larger than the first circumference.

16. The method of claim 13 , wherein the first non-planar stack of materials and the second non-planar stack of materials are cylindrical in shape, or wherein the first non-planar stack of materials and the second non-planar stack of materials are square or square-like in shape.

17. The method of claim 13 , wherein an effective capacitance of the second non-planar stack of materials is substantially equal to a linear component of a capacitance of the first non-planar stack of materials.

18. The method of claim 13 comprising applying a second voltage on the second plate-line, wherein the second voltage on the second plate-line is opposite to a first voltage applied to the first non-planar stack of materials via the first plate-line to compensate for dielectric capacitor dependent charge.

19. The method of claim 13 , wherein the second plate-line has a second voltage which is complementary to a first voltage on the first plate-line.

20. A method comprising:

forming a memory;

storing one or more instructions on the memory;

executing, by a processor circuitry, the one or more instructions; and

allowing, via a communication interface, the processor circuitry to communicate with another device, wherein forming the memory includes:

forming a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, and wherein the via couples to a first metal layer;

forming a first capacitor including a non-linear polar material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is in a middle of the first capacitor;

forming a second capacitor including a linear dielectric material, wherein the electrode passes through a middle of the second capacitor;

forming a first plate-line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first plate-line is on first outer portion of the first capacitor; and

forming a second plate-line extending along the x-plane or the z-plane, wherein the second plate-line is on second output portion of the second capacitor, and wherein the second plate-line has a second voltage complementary to a first voltage on the first plate-line.