Concurrent processing of translation entry invalidation requests in a processor core

1. A method of processing in a processing unit of a data processing system, the method comprising:

buffering, in a data structure in a processor core, a plurality of entries including address translation information;

concurrently processing in the processor core a plurality of translation invalidation requests including at least first and second translation invalidation requests respectively specifying different first and second addresses, wherein the concurrently processing includes checking each of the first and second addresses against all of the plurality of entries in the data structure, and wherein the checking includes:

accessing and checking at least a first entry among the plurality of entries in the data structure for an address match with the first address but not the second address;

thereafter, accessing at least a second entry among the plurality of entries in the data structure and concurrently checking said at least second entry for an address match with both the first and second addresses;

thereafter, completing checking against the plurality of entries for the first address and accessing and checking the first entry for an address match with the second address but not the first address; and

invalidating any entry in the data structure for which the checking detects an address match.

2. The method of claim 1 , wherein the buffering includes buffering the plurality of entries in a directory of an upper level effective address (EA)-based cache holding operand data for access by the processor core.

3. The method of claim 1 , wherein the buffering includes buffering the plurality of entries in a translation lookaside buffer (TLB).

4. The method of claim 1 , further comprising:

buffering, within a queue in the processing unit, a plurality of memory-referent requests, wherein the buffering includes buffering each of the plurality of memory-referent requests in association with a respective one of a plurality of pointers to a corresponding entry in the data structure;

based on the checking, precisely marking in the queue memory-referent requests having pointers to entries of the data structure for which address matches are found; and

controlling timing of completion of the plurality of translation invalidation requests based on the marking, such that each translation invalidation request completes with reference to the processor core only after each memory-referent request indicated by the marking as dependent upon an address translation to be invalidated by said each translation invalidation request has drained from the processing unit.

5. The method of claim 4 , wherein:

the data structure is set-associative; and

each of the plurality of pointers identifies a congruence class and way of the corresponding entry.

6. The method of claim 4 , wherein the queue is one of a load miss queue, a load reorder queue, and a store queue.

7. A processing unit for a data processing system, the processing unit comprising:

an execution unit that executes a memory-referent instruction to calculate a target effective address (EA) of a corresponding memory-referent request;

a data structure that buffers a plurality of entries including address translation information;

translation sequencing logic that is configured to perform:

concurrently processing a plurality of translation invalidation requests including at least first and second translation invalidation requests respectively specifying different first and second addresses, wherein the translation sequencing logic concurrently processing includes checking each of the first and second addresses against all of the plurality of entries in the data structure, and wherein the checking includes:

accessing and checking at least a first entry among the plurality of entries in the data structure for an address match with the first address but not the second address;

thereafter, accessing at least a second entry among the plurality of entries in the data structure and concurrently checking said at least second entry for an address match with both the first and second addresses;

thereafter, completing checking against the plurality of entries for the first address and accessing and checking the first entry for an address match with the second address but not the first address; and

invalidating any entry in the data structure for which the checking detects an address match.

8. The processing unit of claim 7 , wherein the data structure comprises a directory of an upper level effective address (EA)-based cache holding operand data for access by the processing unit.

9. The processing unit of claim 7 , wherein the data structure comprises a translation lookaside buffer (TLB).

10. The processing unit of claim 7 , further comprising:

a queue in the processing unit that buffers a plurality of memory-referent requests, wherein each of the plurality of memory-referent requests is buffered in association with a respective one of a plurality of pointers to a corresponding entry in the data structure;

wherein the translation sequencing logic is further configured to perform:

based on the checking, precisely marking in the queue memory-referent requests having pointers to entries of the data structure for which address matches are found; and

controlling timing of completion of the plurality of translation invalidation requests based on the marking, such that each translation invalidation request completes only after each memory-referent request indicated by the marking as dependent upon an address translation to be invalidated by said each translation invalidation request has drained from the processing unit.

11. The processing unit of claim 10 , wherein:

the data structure is set-associative; and

each of the plurality of pointers identifies a congruence class and way of the corresponding entry.

12. The processing unit of claim 10 , wherein the queue is one of a load miss queue, a load reorder queue, and a store queue.

13. A data processing system including a plurality of processing units according to claim 7 and a system fabric coupling the plurality of processing units.

14. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit including:

an execution unit that executes a memory-referent instruction to calculate a target effective address (EA) of a corresponding memory-referent request;

a data structure that buffers a plurality of entries including address translation information;

translation sequencing logic that is configured to perform:

concurrently processing a plurality of translation invalidation requests including at least first and second translation invalidation requests respectively specifying different first and second addresses, wherein the translation sequencing logic concurrently processing includes checking each of the first and second addresses against all of the plurality of entries in the data structure, and wherein the checking includes:

accessing and checking at least a first entry among the plurality of entries in the data structure for an address match with the first address but not the second address;

thereafter, accessing at least a second entry among the plurality of entries in the data structure and concurrently checking said at least second entry for an address match with both the first and second addresses;

thereafter, completing checking against the plurality of entries for the first address and accessing and checking the first entry for an address match with the second address but not the first address; and

invalidating any entry in the data structure for which the checking detects an address match.

15. The design structure of claim 14 , wherein the data structure comprises a directory of an upper level effective address (EA)-based cache holding operand data for access by the processing unit.

16. The design structure of claim 14 , wherein the data structure comprises a translation lookaside buffer (TLB).

17. The design structure of claim 14 , further comprising:

a queue in the processing unit that buffers a plurality of memory-referent requests, wherein each of the plurality of memory-referent requests is buffered in association with a respective one of a plurality of pointers to a corresponding entry in the data structure;

wherein the translation sequencing logic is further configured to perform:

based on the checking, precisely marking in the queue memory-referent requests having pointers to entries of the data structure for which address matches are found; and

controlling timing of completion of the plurality of translation invalidation requests based on the marking, such that each translation invalidation request completes only after each memory-referent request indicated by the marking as dependent upon an address translation to be invalidated by said each translation invalidation request has drained from the processing unit.

18. The design structure of claim 17 , wherein:

the data structure is set-associative; and

each of the plurality of pointers identifies a congruence class and way of the corresponding entry.

19. The design structure of claim 17 , wherein the queue is one of a load miss queue, a load reorder queue, and a store queue.