Multi-stage bit line pre-charge
Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.
1. A memory circuit, comprising:
a bit cell responsive to a bit line signal line and a bit line bar signal line and configured to store a bit of data; and
a pre-charge circuit configured to charge one of the bit line and bit line bar signal lines prior to a next read operation, wherein the pre-charge circuit comprises:
a first pre-charge component; and
a second pre-charge component;
wherein:
the first and second pre-charge components are individually controllable for charging the bit line and bit line bar signal lines;
the first pre-charge component is configured to charge at a first average rate and the second pre-charge component is configured to charge, alone or in combination with the first pre-charge component, at a second average rate, the second average rate being faster than the first average rate; and
the first pre-charge component comprises a first transistor having a first source/drain terminal connected to both the bit line signal line and the bit line bar signal line.
2. The memory circuit of claim 1 , further comprising a pre-charge control circuit configured to provide a first control signal to the first pre-charge component and a second control signal to the second pre-charge component.
3. The memory circuit of claim 2 , wherein the first transistor further has a second source/drain terminal connected to a source node and a gate controlled by the first control signal.
4. The memory of claim 2 , wherein the first pre-charge component further comprises a second transistor connected between a source node and the first transistor and having a gate controlled by the first control signal.
5. The memory of claim 2 , wherein the first pre-charge component further comprises a second transistor connected between a source node and the first transistor, the second transistor has a gate controlled by the first control signal, and the first transistor has a gate connected to both the bit line signal line and the bit line bar signal line.
6. The memory circuit of claim 2 , wherein the first transistor further has a second source/drain terminal configured to receive the second control signal and a gate controlled by the first control signal.
7. The memory circuit of claim 2 , wherein the second pre-charge component comprises two second stage transistors having gates controlled by the second control signal, one second stage transistor is positioned between a source node and a first node, and another second stage transistor is positioned between the source node and a second node.
8. The memory circuit of claim 2 , wherein the pre-charge control circuit is configured to activate the first pre-charge component prior to a word line signal transition indicating a conclusion of a read operation.
9. The memory circuit of claim 8 , wherein the pre-charge control circuit is configured to activate the second pre-charge circuit after the word line signal transition.
10. The memory circuit of claim 1 , wherein the bit cell is a component of a first memory bank;
wherein the first pre-charge component is configured to further operate as a second pre-charge component for a second memory bank.
11. The memory circuit of claim 1 , wherein the pre-charge circuit is associated with a plurality of bit cells, each bit cell being associated with a different data word.
12. The memory circuit of claim 1 , wherein the pre-charge circuit includes more than two pre-charge components.
13. A method of controlling a multi-stage pre-charge circuit having a first pre-charge component and a second pre-charge component for charging one of a bit line signal line and a bit line bar signal line associated with a bit cell prior to a read operation, comprising:
providing a first control signal to the first pre-charge component inhibiting charging during at least a portion of a read operation, wherein a word line associated with the bit cell is activated during the read operation;
providing a second control signal to the second pre-charge component inhibiting charging during at least the portion of a read operation;
transitioning the first control signal to enable charging by the first pre-charge component prior to deactivation of the word line; and
transitioning the second control signal to enable charging by the second pre-charge component after transitioning the first control signal;
wherein the first pre-charge component is configured to charge at a first average rate, the second pre-charge component is configured to charge, alone or in combination with the first pre-charge component, at a second average rate, the second average rate is faster than the first average rate, and the first pre-charge component comprises a transistor having a source/drain terminal connected to both the bit line signal line and the bit line bar signal line.
14. The method of claim 13 , wherein the first pre-charge component charges at the first average rate when enabled and the second pre-charge component charges at the second average rate when enabled.
15. The method of claim 14 , wherein one of the bit line and bit line bar signal lines transitions to a low state based on a state of the bit cell during the read operation;
wherein enabling the first pre-charge component initializes returning of the one of the bit line and bit line bar signal lines to a charged state prior to a next read operation.
16. The method of claim 13 , wherein the second control signal is transitioned after deactivation of the word line.
17. The method of claim 13 , further comprising:
activating the word line; and
deactivating the word line after said transitioning of the first control signal.
18. The method of claim 13 , wherein the bit line signal line or the bit line bar signal line is charged without changing a state of the bit cell.
19. A memory comprising:
a two-dimensional array of bit cells, each row of bit cells being associated with a data word, each column of bit cells being associated with a multi-stage pre-charge circuit;
a plurality of multi-stage pre-charge circuits; and
a pre-charge control circuit configured to provide a first control signal to first pre-charge components of the pre-charge circuits and a second control signal to second pre-charge components of the pre-charge circuits;
wherein the first pre-charge components are configured to charge at a first average rate, the second pre-charge components are configured to charge, alone or in combination with the first pre-charge components, at a second average rate, the second average rate is faster than the first average rate, and each first pre-charge component comprises a transistor having a source/drain terminal connected to both a bit line signal line and a bit line bar signal line.
20. The memory of claim 19 , wherein:
the first control signal is provided to the first pre-charge components inhibiting charging during at least a portion of a read operation;
a word line associated with a bit cell is activated during the read operation;
the second control signal is provided to the second pre-charge components inhibiting charging during at least the portion of a read operation;
the first control signal is transitioned to enable charging by the first pre-charge components prior to deactivation of the word line; and
the second control signal is transitioned to enable charging by the second-charge components after transitioning the first control signal.