Gate walls for quantum dot devices
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.
1. A quantum dot device, comprising:
a quantum well stack;
a first gate and a second gate above the quantum well stack; and
a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer is in contact with a gate dielectric of the first gate and with a gate dielectric of the second gate, the capping material is in contact with the spacer and the gate dielectric of the second gate, and wherein the quantum well stack is at least partially included in a fin, or the first gate and the second gate are at least partially disposed in a trench in an insulating material above the quantum well stack.
2. The quantum dot device of claim 1 , wherein the spacer includes carbon or wherein the spacer includes nitrogen, silicon, or oxygen.
3. The quantum dot device of claim 1 , wherein the spacer has a material composition different from a material composition of the capping material.
4. The quantum dot device of claim 1 , wherein the capping material includes silicon and oxygen.
5. The quantum dot device of claim 1 , wherein at least some of the spacer is between the capping material and the quantum well stack.
6. The quantum dot device of claim 1 , wherein a height of the capping material is between 5 nanometers and 10 nanometers or wherein a width of the capping material is between 2 nanometers and 10 nanometers.
7. The quantum dot device of claim 1 , wherein the second gate dielectric is at least partially between a gate metal of the second gate and the spacer.
8. The quantum dot device of claim 7 , wherein the capping material is at least partially between the second gate dielectric and the spacer.
9. The quantum dot device of claim 1 , wherein at least a portion of the capping material is conformal on a surface of the spacer.
10. The quantum dot device of claim 1 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device and a non-quantum processing device, coupled to the quantum processing device,
the quantum processing device includes the quantum well stack, the first gate, the second gate, and the gate wall, and
the non-quantum processing device is to control voltages applied to at least one of the first gate and the second gate.
11. The quantum dot device of claim 10 , further comprising:
a memory device to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.
12. The quantum dot device of claim 1 , wherein the spacer separates the capping material and the gate dielectric of the first gate.
13. The quantum dot device of claim 1 , wherein the capping material is vertically aligned with a portion of the spacer that is farthest away from the quantum well stack, and the capping material is separated from the quantum well stack by at least one of: a portion of the spacer and a portion of the gate dielectric of the second gate.
14. The quantum dot device of claim 1 , wherein the gate dielectric of the first gate and the gate dielectric of the second gate are separated by a distance between 1 nanometer and 10 nanometers.
15. The quantum dot device of claim 1 , further comprising:
a first doped region proximate a first end of the quantum well stack; and
a second doped region proximate a second end of the quantum well stack, wherein the second end of the quantum well stack is opposite the first end of quantum well stack,
wherein the first gate and the second gate are over a continuous portion of the quantum well stack between the first doped region and the second doped region.
16. The quantum dot device of claim 15 , wherein a dopant concentration in the first doped region and in the second doped region is higher than a dopant concentration in the continuous portion of the quantum well stack between the first doped region and the second doped region.
17. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes:
a quantum well layer,
a plurality of gates above different portions of the quantum well layer to control quantum dot formation in the quantum well layer, wherein different portions of the quantum well layer are materially continuous portions of a single quantum well layer, and
a dielectric material structure between a first gate and a second gate of the plurality of gates, wherein the dielectric material structure includes a spacer and a capping material, the capping material and the spacer have different material compositions, and the spacer is in contact with a gate dielectric of the first gate and with a gate dielectric of the second gate; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates.
18. The quantum computing device of claim 17 , further comprising:
a memory device to store data generated by quantum dots formed in the quantum well layer during operation of the quantum processing device.
19. The quantum computing device of claim 17 , wherein the spacer includes nitrogen.
20. The quantum computing device of claim 17 , wherein the capping material is in contact with the spacer and with the gate dielectric of the second gate.
21. A quantum dot device, comprising:
a quantum well stack;
a first gate above a first portion of the quantum well stack;
a second gate above a second portion of the quantum well stack, wherein the first portion of the quantum well stack is materially continuous with the second portion of the quantum well stack; and
a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer is in contact with a gate dielectric of the first gate and with a gate dielectric of the second gate, and the capping material is in contact with the spacer and with the gate dielectric of the second gate.
22. The quantum dot device of claim 21 , wherein the quantum well stack is at least partially included in a fin, or the first gate and the second gate are at least partially disposed in a trench in an insulating material above the quantum well stack.
23. The quantum dot device of claim 21 , wherein the spacer separates the capping material and the gate dielectric of the first gate.
24. The quantum dot device of claim 21 , wherein a dimension of the capping material along a direction perpendicular to a quantum well layer of the quantum well stack is between 5 nanometers and 10 nanometers.
25. The quantum dot device of claim 24 , wherein a top of the capping material is vertically aligned with a top of the spacer.