Memory circuit, memory device and operation method thereof

1. A memory device, comprising:

a storage transistor;

a variable capacitance device electrically connected to a gate of the storage transistor; and

a control transistor electrically connected to the storage transistor in series,

wherein the variable capacitance device comprises:

an upper electrode;

a lower electrode electrically connected to the gate of the storage transistor; and

a variable capacitance layer disposed between the upper electrode and the lower electrode,

wherein the storage transistor comprises:

at least one first gate dielectric layer disposed on an active region;

at least one first gate electrode layer disposed on the at least one first gate dielectric layer, the at least one first gate electrode layer contacting one end of a gate contact plug, and another end of the gate contact plug contacting the lower electrode of the variable capacitance device; and

a first source/drain diffusion region and a second source/drain diffusion region disposed in the active region and positioned at two opposing sides respectively under the at least one first gate electrode layer.

2. The memory device of claim 1 , wherein the variable capacitance layer is a ferroelectric layer.

3. The memory device of claim 1 , further comprising:

a first contact plug having one end contacting the upper electrode; and

a first wire contacting another end of the first contact plug, and the first contact plug positioned between the first wire and the upper electrode.

4. The memory device of claim 1 , further comprising:

a second contact plug having one end contacting the second source/drain diffusion region; and

a second wire contacting another end of the second contact plug, and the second contact plug positioned between the second wire and the second source/drain diffusion region.

5. The memory device of claim 1 , wherein the control transistor and the storage transistor share the first source/drain diffusion region, and the control transistor comprises:

at least one second gate dielectric layer disposed on the active region;

at least one second gate electrode layer disposed on the at least one second gate dielectric layer; and

a third source/drain diffusion region and the first source/drain diffusion region disposed in the active region and positioned at two opposing sides respectively under the at least one second gate electrode layer.

6. The memory device of claim 5 , further comprising:

a third contact plug having one end contacting the third source/drain diffusion region; and

a third wire contacting another end of the third contact plug, the third contact plug positioned between the third wire and the third source/drain diffusion region, wherein the at least one second gate electrode layer of the control transistor serves as a fourth wire.

7. A memory circuit, comprising:

a plurality of memory cells arranged in an array, each of the memory cells comprising a first memory device, and the first memory device comprising:

a first storage transistor having a first gate, a first source/drain and a second source/drain;

a first variable capacitance device having one end electrically connected to the first gate of the first storage transistor; and

a first control transistor having a second gate, a third source/drain and a fourth source/drain, wherein the fourth source/drain of the first control transistor is electrically connected to the first source/drain of the first storage transistor, wherein another end of the first variable capacitance device is electrically connected to a first driver through a first wire, and the second source/drain of the first storage transistor is electrically connected to a second driver through a second wire, the third source/drain of the first control transistor is electrically connected to a third driver through a third wire, and the second gate of the first control transistor is electrically connected to a fourth driver through a fourth wire.

8. The memory circuit of claim 7 , wherein each of the memory cells further comprises a second memory device, and the second memory device comprises:

a second storage transistor having a first gate, a first source/drain and a second source/drain;

a second variable capacitance device having one end electrically connected to the first gate of the second storage transistor; and

a second control transistor having a second gate, a third source/drain and a fourth source/drain, wherein the fourth source/drain of the second control transistor is electrically connected the first source/drain of the second storage transistor.

9. The memory circuit of claim 8 , wherein another of the second variable capacitance device is electrically connected to the first driver through the first wire, the second source/drain of the second storage transistor is electrically connected to the second driver through the second wire, the third source/drain of the second control transistor is electrically connected to the third driver through the third wire, and the second gate of the second control transistor is electrically connected to the fourth driver through another fourth wire.

10. The memory circuit of claim 9 , wherein the first storage transistor is adjacent to the second storage transistor, and the first and second storage transistors are positioned between the first control transistor and the second control transistor, and the second wire is positioned between the fourth wire and the another fourth wire.

11. An operation method of a memory device, the memory device comprising a storage transistor, a variable capacitance device and a control transistor, the operation method comprising steps of:

when programming the memory device, applying a control voltage to a control line, applying a programming voltage to a bit line, applying a zero voltage to a word line, and floating a ground line, wherein one end of the variable capacitance device is electrically connected to a first gate of the storage transistor, another end of the variable capacitance device is electrically connected to the word line, a first source/drain electrode of the storage transistor is electrically connected to a fourth source/drain of the control transistor, a second source/drain of the storage transistor electrically connected to the ground line, a third source/drain of the control transistor electrically connected to the bit line, and a second gate of the control transistor is electrically connected to the control line.

12. The operation method of claim 11 , wherein the programming voltage is greater than the control voltage, and the control voltage is greater than the zero voltage.

13. The operation method of claim 11 , further comprising:

when erasing the memory device, applying the control voltage to the control line, applying the zero voltage to the bit line, applying an erasing voltage to the word line, and floating the ground line.

14. The operation method of claim 13 , wherein the erasing voltage is greater than the control voltage, and the control voltage is greater than the zero voltage.

15. The operation method of claim 13 , further comprising:

when reading the memory device, applying an operating voltage to the control line, applying 0.1 times to 1.5 times the operating voltage to the bit line, applying a read voltage to the word line, and applying the zero voltage to the ground line.

16. The operation method of claim 15 , wherein the read voltage is lower than the programming voltage, and the read voltage is lower than the erasing voltage.

17. The operation method of claim 11 , further comprising:

when the memory device is not selected, applying the zero voltage to the control line, the bit line, the word line and the ground line.

18. The operation method of claim 11 , further comprising:

when refreshing the memory device, periodically programming the memory device every predetermined time.