Digital signal processing system
A digital signal processing system for multiplying a digital value and a digital signal. The digital signal processing system receives the digital value in an encoded format, and multiplies the digital value with the digital signal. The digital value in the encoded format has an offset, which is encoded as a floating point. The disclosure provides a digital processing system that can carry out a multiplication operation with a smaller area, less complexity and/or reduced power usage compared with known multipliers.
1. A digital signal processing system for multiplying a digital value and a digital signal, the digital signal processing system configured to:
receive the digital value in an encoded format; and:
multiply the digital value with the digital signal; wherein:
the digital value in the encoded format comprises twenty four bits and an offset, the offset being encoded as a floating point.
2. The digital signal processing system of claim 1 , wherein a base of the floating point is two.
3. The digital signal processing system of claim 1 , wherein the floating point comprises a fractional part and an exponent.
4. The digital signal processing system of claim 3 , wherein the fractional part comprises a sign bit and a mantissa.
5. The digital signal processing system of claim 4 , wherein:
the exponent comprises four bits; and/or
the fractional part comprises twenty bits.
6. The digital signal processing system of claim 1 , wherein the digital value in the encoded format comprises an integer.
7. The digital signal processing system of claim 6 , wherein the integer comprises two bits.
8. The digital signal processing system of claim 7 , wherein:
the floating point comprises a fractional part and an exponent; and
the exponent comprises four bits and/or the fractional part comprises eighteen bits.
9. The digital signal processing system of claim 1 , comprising:
a decoding circuit configured to
i) receive the digital value in the encoded format; and
ii) decode the digital value prior to multiplication; and
a multiplication circuit configured to:
i) receive the digital value in a decoded format; and
ii) to multiply the digital value in the decoded format with the digital signal.
10. The digital signal processing system of claim 9 , wherein the floating point comprises a fractional part and an exponent.
11. The digital signal processing system of claim 10 , wherein the digital value in the encoded format comprises an integer.
12. The digital signal processing system of claim 11 , wherein the decoding circuit is configured to provide the digital value in the decoded format by providing:
a first component comprising the integer in the decoded format;
a second component comprising the fractional part in the decoded format; and
a third component comprising the exponent in the decoded format.
13. The digital signal processing system of claim 12 , wherein the multiplication circuit comprises:
a first multiplier configured to receive the first component and the digital signal;
a second multiplier configured to receive the second component and the digital signal; and
a shifter circuit configured to receive the third component.
14. The digital signal processing system of claim 13 , wherein the multiplication circuit comprises an addition circuit, wherein:
the first multiplier is configured to multiply the first component and the digital signal and to provide a first output to the addition circuit;
the second multiplier is configured to multiply the second component and the digital signal and to provide a second output to the shifter circuit;
the shifter circuit is configured to shift the second output using the third component and to provide a third output to the addition circuit; and
the addition circuit is configured to add the first output and the third output to provide a fourth output, the fourth output being the multiplication of the digital value and the digital signal.
15. The digital signal processing system of claim 1 wherein the digital signal comprises thirty two bits.
16. The digital signal processing system of claim 1 comprising a memory element configured to store the digital value in the encoded format.
17. The digital signal processing system of claim 1 configured to processes digital signal at an oversampled rate.
18. A multiply accumulate unit comprising a digital signal processing system for multiplying a digital value and a digital signal, the digital signal processing system configured to:
receive the digital value in an encoded format; and
multiply the digital value with the digital signal; wherein:
the digital value in the encoded format comprises twenty four bits and an offset, the offset being encoded as a floating point.
19. An active noise cancellation system comprising a digital signal processing system configured as a noise cancelling filter, the digital signal processing system for multiplying a digital value and a digital signal wherein the digital signal is an audio signal, the digital signal processing system configured to:
receive the digital value in an encoded format; and:
multiply the digital value with the digital signal; wherein:
the digital value in the encoded format comprises an offset, the offset being encoded as a floating point.
20. The active noise cancellation system of claim 19 , wherein the active noise cancellation system is implemented within a headset.
21. A method for multiplying a digital value and a digital signal using a digital signal processing system, the method comprising:
receiving the digital value in an encoded format using the digital signal processing system; and:
multiplying the digital value with the digital signal using the digital signal processing system; wherein:
the digital value in the encoded format comprises twenty four bits and an offset, the offset being encoded as a floating point.