System and method for secure, fast communications between processors on complex chips
A system and method for fast communication between processors on complex chips using encoding, wherein a training data set is used to find patterns and associated smaller indices, or codewords, which are stored in a reference codebook library, and where reconstruction and deconstruction algorithms are used to encode and decode data as it is received. The codebook and algorithms may be stored in the firmware of a semiconductor which enable reduced resources and cost when transmitting data between or among devices that utilize such semiconductors.
1. A system for secure and fast communication between processors on complex chips, comprising:
a complex chip comprising at least two processors and a memory for each processor;
wherein each of a first processor and a second processor on the complex chip stores a pre-trained reference codebook embedded as firmware in its respective memory, wherein:
the pre-trained reference codebook is generated by using training data to identify chunklets and their associated codewords, and storing the associated codewords in the pre-trained reference codebook; and
codewords within the pre-trained reference codebook are assigned such that more frequently-occurring chunklets are assigned shorter codewords based on a combination of:
an observed frequency of occurrence of chunklets in the training data; and
an estimated frequency of occurrence of chunklets not in the training;
wherein each of a first processor and a second processor on the complex chip stores a deconstruction algorithm embedded as firmware in in its respective memory, wherein the deconstruction algorithm, when operating on the first processor, causes the first processor to:
receive data;
deconstruct the data into a plurality of chunklets; and
encode the data by retrieving the codeword for each chunklet from the pre-trained reference codebook; and
wherein each of a first processor and a second processor on the complex chip stores a reconstruction algorithm embedded as firmware in in its respective memory, wherein the reconstruction algorithm, when operating on the second processor, causes the second processor to:
receive a codeword;
retrieve a chunklet for each received codeword from the pre-trained reference codebook; and
assemble the chunklets to reconstruct the data.
2. A method for secure and fast communication between processors on complex chips, comprising the steps of:
storing a pre-trained reference codebook embedded as firmware in the memory of a first processor and in the memory of a second processor, wherein:
the pre-trained reference codebook is generated by using training data that identifies chunklets and their associated codewords, and storing the associated codewords in the pre-trained reference codebook; and
codewords within the pre-trained reference codebook are assigned such that more frequently-occurring chunklets are assigned shorter codewords based on a combination of:
an observed frequency of occurrence of chunklets in the training data; and
an estimated frequency of occurrence of chunklets not in the training;
storing a deconstruction algorithm embedded as firmware in the memory of the first processor-and in the memory of the second processor, wherein the deconstruction algorithm, when operating on the first processor, causes the first processor to:
receive data;
deconstruct the data into a plurality of chunklets; and
encode the data by retrieving the codeword for each chunklet from the pre-trained reference codebook; and
storing a reconstruction algorithm embedded as firmware in the memory of the first processor and in the memory of the second processor, wherein the reconstruction algorithm, when operating on the second processor, causes the second processor to:
receiving a codeword;
retrieving the chunklet for each received codeword from the pre-trained reference codebook; and
assembling the chunklets to reconstruct the data.