Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device comprising: a substrate; a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate; and a word line cut region which extends in a second direction different from the first direction and cuts the mold structure, wherein the word line cut region includes a common source line, and the common source line includes a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and being in contact with the second insulating pattern and a cross-section in the second direction.
1. A nonvolatile memory device comprising:
a substrate;
a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate; and
a word line cut region which extends in a second direction different from the first direction and cuts the mold structure,
wherein the word line cut region includes a common source line and source line spacer, and
the common source line includes a common source line insulating pattern extending in the second direction in an extension region of the mold structure, and a conductive pattern extending in the second direction in a cell array region of the mold structure, the conductive pattern being in contact with the common source line insulating pattern and a cross-section in the second direction.
2. The nonvolatile memory device of claim 1 , wherein the common source line insulating pattern includes a first sub-insulating pattern and a second sub-insulating pattern spaced apart in the second direction, and
a gate electrode of the plurality of gate electrodes, around the first sub-insulating pattern and the second sub-insulating pattern, has an H shape.
3. The nonvolatile memory device of claim 1 , wherein the common source line insulating pattern includes an air gap.
4. The nonvolatile memory device of claim 1 , wherein a peripheral circuit structure including a peripheral circuit element electrically connected to the mold structure is below the substrate.
5. The nonvolatile memory device of claim 1 , wherein the common source line insulating pattern includes an amorphous carbon layer (ACL).
6. The nonvolatile memory device of claim 1 , wherein the common source line insulating pattern includes a spin-on hard mask (SOH).
7. A nonvolatile memory device comprising:
a substrate;
a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked on the substrate in a first direction;
a plurality of channel structures penetrating the mold structure;
a plurality of pad electrodes which is electrically connected to the plurality of channel structures to provide a voltage; and
a plurality of word line cut regions which extends in a second direction different from the first direction and cuts the mold structure,
wherein each of the plurality of word line cut regions includes a common source line,
each of the common source lines includes a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and being in contact with the second insulating pattern and a cross-section in the second direction, and
a lowermost part in the first direction of at least one of the common source lines is spaced apart from a gate electrode stacked at a lowermost part in the first direction of the plurality of gate electrodes in the first direction.
8. The nonvolatile memory device of claim 7 , the mold structure includes a cell array region, and an extension region having a staircase structure,
the second insulating pattern is in the extension region of the mold structure.
9. The nonvolatile memory device of claim 8 , wherein the cell array region of the mold structure is in the conductive pattern.
10. The nonvolatile memory device of claim 7 , wherein the second insulating pattern includes a first sub-insulating pattern and a second sub-insulating pattern spaced apart in the second direction, and
the gate electrode around the first sub-insulating pattern and the second sub-insulating pattern has an H shape.
11. The nonvolatile memory device of claim 7 , wherein the second insulating pattern includes an air gap.
12. The nonvolatile memory device of claim 7 , wherein the second insulating pattern includes an amorphous carbon layer.
13. The nonvolatile memory device of claim 7 , wherein the second insulating pattern includes a spin-on hard mask.
14. The nonvolatile memory device of claim 7 , wherein at least one of the common source lines is adjacent to the plurality of pad electrodes.
15. A nonvolatile memory device comprising:
a substrate;
a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked on the substrate in a first direction;
a plurality of channel structures penetrating the mold structure, each of the plurality of channel structures including, at a lowermost stage, a first semiconductor pattern, an information storage film for exposing the first semiconductor pattern, a second semiconductor pattern along the information storage film and the first semiconductor pattern, a filling pattern in the second semiconductor pattern, and a channel pad on the information storage film, the second semiconductor pattern, and the filling pattern;
a word line cut region which extends along a second direction different from the first direction and cuts the mold structure, the word line cut region including a common source line spacer which is along a sidewall of the word line cut region and exposes the substrate, and a common source line inside the common source line spacer, the common source line including a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and being in contact with the second insulating pattern and a cross-section in the second direction;
a first interlayer insulating film which is on the mold structure and surrounds at least some of the plurality of channel structures and at least a part of the word line cut region;
a bit line contact on the channel pad;
a second interlayer insulating film which surrounds the bit line contact; and
a bit line formed on the second interlayer insulating film and electrically connected to the bit line contact.
16. The nonvolatile memory device of claim 15 , wherein the second insulating pattern includes an air gap.
17. The nonvolatile memory device of claim 15 , wherein the second insulating pattern includes an amorphous carbon layer.
18. The nonvolatile memory device of claim 15 , wherein the second insulating pattern includes a spin-on hard mask.