Digital-to-analog converter (DAC) architecture optimization
A digital-to-analog converter (DAC) comprises circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2 N −1, and circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.
1. A digital-to-analog converter (DAC) comprising:
circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2 N −1; and
circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein a weight ratio of at least one pair of the weighted current sources is a positive real number different from an integer power of two.
2. The DAC as claimed in claim 1 , wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.
3. The DAC as claimed in claim 2 , wherein the at least one error metric represents errors caused by statistical rise/fall asymmetry between currents flowing from the weighted current sources.
4. The DAC as claimed in claim 2 , wherein the at least one error metric represents errors caused by statistical amplitude mismatches between currents flowing from the weighted current sources.
5. The DAC as claimed in claim 2 , wherein the at least one error metric represents errors caused by statistical timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.
6. The DAC as claimed in claim 2 , wherein the mapping is configured to minimize the at least one error metric.
7. The DAC as claimed in claim 2 , wherein the mapping is configured to minimize a DAC-specific error metric representing errors caused by circuit component mismatches measured in the DAC.
8. The DAC as claimed in claim 7 , wherein the circuit component mismatches comprise one or more of
rise/fall asymmetry between currents flowing from the weighted current sources;
amplitude mismatches between currents flowing from the weighted current sources; and
timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.
9. The DAC as claimed in claim 1 , wherein weights of the weighted current sources do not solely consist of a combination of unary weights and binary weights.
10. The DAC as claimed in claim 1 , wherein the digital input comprises a pre-compensated digital signal generated based on a distortion model representing circuit component mismatches in the DAC.
11. A method for digital-to-analog conversion comprising:
generating, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2 N −1; and
controlling current flow from L weighted current sources of a digital-to-analog converter (DAC) using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein a weight ratio of at least one pair of the weighted current sources is a positive real number different from an integer power of two.
12. The method as claimed in claim 11 , wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.
13. The method as claimed in claim 12 , wherein the at least one error metric represents glitch errors caused by statistical rise/fall asymmetry between currents flowing from the weighted current sources.
14. The method as claimed in claim 12 , wherein the at least one error metric represents errors caused by statistical amplitude mismatches between currents flowing from the weighted current sources.
15. The method as claimed in claim 12 , wherein the at least one error metric represents glitch errors caused by statistical timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.
16. The method as claimed in claim 12 , wherein the mapping is configured to minimize the at least one error metric.
17. The method as claimed in claim 12 , further comprising calculating the mapping by minimizing a DAC-specific error metric representing errors caused by circuit component mismatches measured in the DAC.
18. The method as claimed in claim 17 , wherein the circuit component mismatches comprise one or more of
rise/fall asymmetry between currents flowing from the weighted current sources;
amplitude mismatches between currents flowing from the weighted current sources; and
timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.
19. The method as claimed in claim 11 , wherein weights of the weighted current sources do not solely consist of a combination of unary weights and binary weights.
20. The method as claimed in claim 11 , wherein the digital input comprises a pre-compensated digital signal generated based on a distortion model representing circuit component mismatches in the DAC.