ESD protection apparatus and control method

1. An apparatus comprising:

a discharge resistor and a transistor connected in series between a first voltage rail and a second voltage rail;

a first coupling capacitor and a diode connected in series between the first voltage rail and a gate of the transistor, wherein an anode of the diode is connected to the first coupling capacitor, and a cathode of the diode is connected to the gate of the transistor;

an auxiliary transistor connected between the gate of the transistor and ground; and

an ESD protection device connected between the first voltage rail and the second voltage rail.

2. The apparatus of claim 1 , wherein:

the first voltage rail is an ESD rail; and

the second voltage rail is connected to ground.

3. The apparatus of claim 1 , further comprising:

a first bias resistor connected in parallel with the auxiliary transistor, wherein the first bias resistor is configured to discharge the gate of the transistor in a controllable manner so as to control an on time of the transistor.

4. The apparatus of claim 1 , wherein:

the transistor is an n-type transistor having a drain connected to the discharge resistor and a source connected to ground.

5. The apparatus of claim 1 , wherein the ESD protection device comprises:

an ESD transistor connected between the first voltage rail and the second voltage rail;

a drive transistor and a second bias resistor connected in series between the first voltage rail and the second voltage rail, and wherein a common node of the drive transistor and the second bias resistor is connected to a gate of the ESD transistor; and

a second coupling capacitor and a third bias resistor connected in series between the first voltage rail and the second voltage rail, and wherein a common node of the second coupling capacitor and the third bias resistor is connected to a gate of the drive transistor.

6. The apparatus of claim 5 , wherein:

the ESD transistor is an n-type transistor having a drain connected to the first voltage rail and a source connected to the second voltage rail.

7. The apparatus of claim 5 , wherein:

the drive transistor is an n-type transistor having a drain connected to the first voltage rail and a source connected to the second bias resistor.

8. The apparatus of claim 1 , further comprising:

a plurality of first upper diodes connected between the first voltage rail and respective power supply terminals;

a plurality of first lower diodes connected between the respective power supply terminals and the second voltage rail;

a plurality of second upper diodes connected between the first voltage rail and respective signal input/output terminals; and

a plurality of second lower diodes connected between the respective signal input/output terminals and the second voltage rail.

9. The apparatus of claim 8 , wherein:

cathodes of the plurality of first upper diodes are connected to the first voltage rail; and

anodes of the plurality of first lower diodes are connected to the second voltage rail.

10. The apparatus of claim 8 , wherein:

cathodes of the plurality of second upper diodes are connected to the first voltage rail; and

anodes of the plurality of second lower diodes are connected to the second voltage rail.

11. The apparatus of claim 1 , wherein:

the auxiliary transistor is configured to shut down the transistor in response to a shutdown signal.

12. A method comprising:

configuring a discharge device to discharge a voltage on a first voltage rail upon detecting a voltage surge on the first voltage rail, wherein the discharge device comprises a discharge resistor and a transistor connected in series between the first voltage rail and a second voltage rail;

configuring a diode to block a current from flowing from a gate of the transistor to the first voltage rail, wherein an anode of the diode is connected to a first coupling capacitor, and a cathode of the diode is connected to the gate of the transistor; and

configuring a bias resistor or an auxiliary transistor to discharge the gate of the transistor in a controllable manner so as to control an on time of the transistor.

13. The method of claim 12 , further comprising:

configuring an ESD device to discharge the voltage on the first voltage rail upon detecting the voltage surge on the first voltage rail, wherein the ESD device and the discharge device are connected in parallel between the first voltage rail and the second voltage rail.

14. The method of claim 13 , wherein the ESD device comprises:

an ESD transistor connected between the first voltage rail and the second voltage rail;

a drive transistor and a second bias resistor connected in series between the first voltage rail and the second voltage rail, and wherein a common node of the drive transistor and the second bias resistor is connected to a gate of the ESD transistor; and

a second coupling capacitor and a third bias resistor connected in series between the first voltage rail and the second voltage rail, and wherein a common node of the second coupling capacitor and the third bias resistor is connected to a gate of the drive transistor.

15. The method of claim 14 , wherein:

the ESD transistor is an n-type transistor having a drain connected to the first voltage rail and a source connected to the second voltage rail; and

the drive transistor is an n-type transistor having a drain connected to the first voltage rail and a source connected to the second bias resistor.

16. The method of claim 12 , further comprising:

configuring the auxiliary transistor to shut down the transistor in response to a shutdown signal, wherein the auxiliary transistor is connected in parallel with the bias resistor.

17. The method of claim 12 , wherein:

the first coupling capacitor, the diode and the bias resistor are connected in series between the first voltage rail and the second voltage rail, and wherein a common node of the diode and the bias resistor is connected to the gate of the transistor, and wherein:

the first voltage rail is an ESD rail;

the second voltage rail is connected to ground;

the transistor is an n-type transistor having a drain connected to the discharge resistor and a source connected to ground.

18. A semiconductor chip comprising:

a plurality of power supply terminals;

a plurality of first upper diodes and a plurality of first lower diodes connected in series between a first voltage rail and a second voltage rail, wherein a common node of a first upper diode and a first lower diode adjacent to the first upper diode is connected to a corresponding power supply terminal;

a plurality of signal input/output terminals;

a plurality of second upper diodes and a plurality of second lower diodes connected in series between the first voltage rail and the second voltage rail, wherein a common node of a second upper diode and a second lower diode adjacent to the second upper diode is connected to a corresponding signal input/output terminal;

an ESD protection device connected between the first voltage rail and the second voltage rail; and

an auxiliary ESD protection device connected between the first voltage rail and the second voltage rail, wherein in response to a voltage surge on the first voltage rail, an on time of the auxiliary ESD protection device is greater than an on time of the ESD protection device, wherein the auxiliary ESD protection device comprises a discharge resistor and a transistor connected in series between the first voltage rail and the second voltage rail, and a first coupling capacitor and a diode connected in series between the first voltage rail and a gate of the transistor, and wherein an anode of the diode is connected to the first coupling capacitor, and a cathode of the diode is connected to the gate of the transistor.

19. The semiconductor chip of claim 18 , wherein

the first coupling capacitor, the diode and an auxiliary transistor are connected in series between the first voltage rail and the second voltage rail, wherein a common node of the diode and the auxiliary transistor is connected to the gate of the transistor, and wherein the auxiliary transistor is configured to shut down the transistor in response to a shutdown signal.

20. The semiconductor chip of claim 18 , wherein the ESD protection device comprises:

an ESD transistor connected between the first voltage rail and the second voltage rail;

a drive transistor and a second bias resistor connected in series between the first voltage rail and the second voltage rail, and wherein a common node of the drive transistor and the second bias resistor is connected to a gate of the ESD transistor; and

a second coupling capacitor and a third bias resistor connected in series between the first voltage rail and the second voltage rail, and wherein a common node of the second coupling capacitor and the third bias resistor is connected to a gate of the drive transistor.