Microprocessor that prevents same address load-load ordering violations
A microprocessor prevents same address load-load ordering violations. Each load queue entry holds a load physical memory line address (PMLA) and an indication of whether a load instruction has completed execution. The microprocessor fills a line specified by a fill PMLA into a cache entry and snoops the load queue with the fill PMLA, either before the fill or in an atomic manner with the fill with respect to ability of the filled entry to be hit upon by any load instruction, to determine whether the fill PMLA matches load PMLAs in load queue entries associated with load instructions that have completed execution and there are other load instructions in the load queue that have not completed execution. The microprocessor, if the condition is true, flushes at least the other load instructions in the load queue that have not completed execution.
1. A microprocessor that prevents same address load-load ordering violations, comprising:
a cache;
a load queue, wherein each entry of the load queue is configured to hold:
a load physical memory line address associated with a load instruction; and
an indication of whether the load instruction has completed execution;
wherein the microprocessor is configured to:
perform a fill of a copy of a line of memory specified by a fill physical memory line address into an entry of the cache;
perform a snoop of the load queue with the fill physical memory line address, wherein the snoop is performed either before the fill or in an atomic manner with the fill, wherein the atomic manner is with respect to ability of the filled entry to be hit upon by any load instruction;
determine, based on the snoop, whether a condition is true, wherein the condition comprises:
the fill physical memory line address matches one or more load physical memory line addresses in one or more entries of the load queue associated with one or more load instructions that have completed execution; and
there are one or more other load instructions in the load queue that have not completed execution; and
if the condition is true, flush at least the one or more other load instructions in the load queue that have not completed execution.
2. The microprocessor of claim 1 , further comprising:
wherein the microprocessor is absent logic configured to check for same address load-load ordering violations during execution of load instructions.
3. The microprocessor of claim 1 , further comprising:
wherein the load instruction has completed execution when the load physical memory line address has been written to the entry of the load queue associated with the load instruction.
4. The microprocessor of claim 3 , further comprising:
wherein the load instruction has completed execution further when load data has been provided to the load instruction.
5. The microprocessor of claim 3 , further comprising:
wherein each valid entry of the cache holds a physical memory line address of a cache line stored in the valid entry; and
wherein the microprocessor is further configured to, during execution of the load instruction, receive the load physical memory line address from the cache and write the load physical memory line address to the entry of the load queue associated with the load instruction and set the indication that the load instruction has completed execution.
6. The microprocessor of claim 3 ,
a translation lookaside buffer (TLB) accessed by a virtual address specified by the load instruction; and
wherein the microprocessor is further configured to, during execution of the load instruction, receive the load physical memory line address from the TLB and write the load physical memory line address to the entry of the load queue associated with the load instruction and set the indication that the load instruction has completed execution.
7. The microprocessor of claim 1 ,
wherein the cache is virtually-indexed and virtually-tagged.
8. The microprocessor of claim 1 , further comprising:
wherein to flush at least the one or more other load instructions in the load queue that have not completed execution, the control logic is configured to determine a flush boundary and to flush all instructions younger than the flush boundary.
9. The microprocessor of claim 8 ,
wherein the flush boundary is determined to be before an oldest load instruction in the load queue that has not completed execution.
10. The microprocessor of claim 8 ,
wherein the flush boundary is determined to be before an oldest load/store instruction in the load queue or a store queue that has not completed execution.
11. The microprocessor of claim 1 , further comprising:
wherein the microprocessor is configured to concurrently execute N load instructions, wherein N is greater than one; and
wherein the load queue comprises a content-addressable memory (CAM) and has fewer than N CAM ports.
12. The microprocessor of claim 1 ,
wherein the condition further comprises: among the one or more load instructions that have completed execution whose load physical memory line address matches the fill physical memory line address, at least one of them is younger than an oldest load instruction in the load queue that has not completed execution.
13. A method that prevents same address load-load ordering violations, comprising:
in a microprocessor comprising:
a cache; and
a load queue, wherein each entry of the load queue is configured to hold:
a load physical memory line address associated with a load instruction; and
an indication of whether the load instruction has completed execution;
performing a fill of a copy of a line of memory specified by a fill physical memory line address into an entry of the cache;
performing a snoop of the load queue with the fill physical memory line address, wherein the snoop is performed either before the fill or in an atomic manner with the fill, wherein the atomic manner is with respect to ability of the filled entry to be hit upon by any load instruction;
determining, based on the snoop, whether a condition is true, wherein the condition comprises:
the fill physical memory line address matches one or more load physical memory line addresses in one or more entries of the load queue associated with one or more load instructions that have completed execution; and
there are one or more other load instructions in the load queue that have not completed execution; and
if the condition is true, flushing at least the one or more other load instructions in the load queue that have not completed execution.
14. The method of claim 13 , further comprising:
wherein the microprocessor is absent logic configured to check for same address load-load ordering violations during execution of load instructions.
15. The method of claim 13 , further comprising:
wherein the load instruction has completed execution when the load physical memory line address has been written to the entry of the load queue associated with the load instruction.
16. The method of claim 15 , further comprising:
wherein the load instruction has completed execution further when load data has been provided to the load instruction.
17. The method of claim 15 , further comprising:
wherein each valid entry of the cache holds a physical memory line address of a cache line stored in the valid entry; and
receiving, during execution of the load instruction, the load physical memory line address from the cache and writing the load physical memory line address to the entry of the load queue associated with the load instruction and setting the indication that the load instruction has completed execution.
18. The method of claim 15 ,
a translation lookaside buffer (TLB) accessed by a virtual address specified by the load instruction; and
receiving, during execution of the load instruction, the load physical memory line address from the TLB and writing the load physical memory line address to the entry of the load queue associated with the load instruction and setting the indication that the load instruction has completed execution.
19. The method of claim 13 ,
wherein the cache is virtually-indexed and virtually-tagged.
20. The method of claim 13 , further comprising:
wherein said flushing at least the one or more other load instructions in the load queue that have not completed execution comprises determining a flush boundary and flushing all instructions younger than the flush boundary.
21. The method of claim 20 ,
wherein the flush boundary is determined to be before an oldest load instruction in the load queue that has not completed execution.
22. The method of claim 20 ,
wherein the flush boundary is determined to be before an oldest load/store instruction in the load queue or a store queue that has not completed execution.
23. The method of claim 13 ,
wherein the condition further comprises: among the one or more load instructions that have completed execution whose load physical memory line address matches the fill physical memory line address, at least one of them is younger than an oldest load instruction in the load queue that has not completed execution.
24. A microprocessor that prevents same address load-load ordering violations, comprising:
a cache configured to pick an entry of the cache to fill with a copy of a line of memory specified by a fill physical memory line address;
a load queue, wherein each entry of the load queue is configured to hold:
a load physical memory line address associated with a load instruction; and
an indication of whether the load instruction has completed execution;
wherein the microprocessor is configured to:
perform a fill of the copy of the line of memory into the picked entry of the cache;
perform a snoop of the load queue with the fill physical memory line address;
determine, based on the snoop, whether a condition is true, wherein the condition comprises the fill physical memory line address matches one or more load physical memory line addresses in one or more entries of the load queue associated with one or more load instructions that have completed execution; and
flush, if the condition is true, at least the one or more matching load instructions that have completed execution.
25. The microprocessor of claim 24 , further comprising:
wherein the microprocessor is absent logic configured to check for same address load-load ordering violations during execution of load instructions.
26. The microprocessor of claim 24 ,
wherein the cache is virtually-indexed and virtually-tagged.
27. The microprocessor of claim 24 , further comprising:
wherein to flush at least the one or more matching load instructions that have completed execution, the control logic is configured to determine a flush boundary and to flush all instructions younger than the flush boundary; and
wherein the flush boundary is determined to be before an oldest of the one or more matching load instructions that have completed execution.
28. A method that prevents same address load-load ordering violations, comprising:
in a microprocessor comprising:
a cache; and
a load queue, wherein each entry of the load queue is configured to hold:
a load physical memory line address associated with a load instruction; and
an indication of whether the load instruction has completed execution;
performing a fill of a copy of a line of memory specified by a fill physical memory line address into an entry of the cache; and
performing a snoop of the load queue with the fill physical memory line address;
determining, based on the snoop, whether a condition is true, wherein the condition comprises the fill physical memory line address matches one or more load physical memory line addresses in one or more entries of the load queue associated with one or more load instructions that have completed execution; and
flushing, if the condition is true, at least the one or more matching load instructions that have completed execution.
29. The method of claim 28 , further comprising:
wherein the microprocessor is absent logic configured to check for same address load-load ordering violations during execution of load instructions.
30. The method of claim 28 ,
wherein the cache is virtually-indexed and virtually-tagged.
31. The method of claim 28 , further comprising:
wherein said flushing at least the one or more matching load instructions that have completed execution comprises determining a flush boundary and flushing all instructions younger than the flush boundary; and
wherein the flush boundary is determined to be before an oldest of the one or more matching load instructions that have completed execution.