Buffer control of multiple memory banks

1. A system comprising:

a plurality of memory banks;

a plurality of buffers, wherein each of the plurality of buffers is to perform a write process to write data to a corresponding one of the plurality of memory banks; and

a buffer controller including:

a first register to store an address of a corresponding memory bank of the plurality of memory banks,

a second register indicating a first entry storing an address of a memory bank on which the write process is predicted to be completed next among the plurality of memory banks,

a third register indicating a second entry to be updated, and

a controller to configure one or more buffers of the plurality of buffers to perform the write process, according to the first and second entries.

2. The system of claim 1 , further comprising:

determining whether updating the first register for a first clock cycle is blocked or unblocked,

updating the second entry indicated by the third register according to an input address of a target memory bank of the plurality of memory banks to store input data through the write process, in response to determining that updating the first register for the first clock cycle is unblocked, and

setting the third register to indicate a third entry subsequent to the second entry, in response to updating the second entry.

3. The system of claim 2 , wherein the controller is to configure the one or more buffers of the plurality of buffers to perform the write process for the first clock cycle according to the updated second entry.

4. The system of claim 3 , wherein the controller is to configure the one or more buffers of the plurality of buffers to perform the write process for the first clock cycle by:

obtaining addresses of a set of memory banks,

identifying one or more memory banks from the set of memory banks, on which the write process has completed, and

configuring the one or more buffers to perform the write process on the one or more memory banks for the first clock cycle.

5. The system of claim 3 , wherein the controller is to determine whether to block updating the first register for a second clock cycle subsequent to the first clock cycle, in response to configuring the one or more buffers of the plurality of buffers to perform the write process for the first clock cycle.

6. The system of claim 5 , wherein the controller is to determine whether to block updating the first register for the second clock cycle by:

comparing the first entry indicated by the second register and the third entry indicated by the third register, and

determining whether to block updating the first register for the second clock cycle according to the comparison.

7. The system of claim 6 , wherein the controller is to determine to block updating the first register for the second clock cycle, in response to the first entry indicated by the second register being equal to the third entry indicated by the third register.

8. The system of claim 6 , wherein the controller is to determine to unblock updating the first register for the second clock cycle, in response to the first entry indicated by the second register and the third entry indicated by the third register being different.

9. The system of claim 1 , wherein the controller is to:

clear the first entry, in response to receiving, from the memory bank, a write complete signal indicating that the write process on the memory bank has completed, and

set the second register to indicate a fourth entry subsequent to the first entry, in response to clearing the first entry.

10. The system of claim 1 , wherein the second register and the third register each include a shift register.

11. A controller having programmed instructions that when executed cause the controller to:

determine whether to block updating a first register for a first clock cycle according to a second register and a third register, wherein the second register indicates a first entry storing an address of a memory bank, on which a write process is predicted to be completed next among a plurality of memory banks, wherein the third register indicates a second entry to be updated;

select, for the first clock cycle, the second entry, in response to determining that updating the first register for the first clock cycle is unblocked; and

update, for the first clock cycle, the second entry according to an input address of a target memory bank of the plurality of memory banks to store input data through the write process.

12. The controller of claim 11 , wherein the instructions when executed further cause the controller to configure one or more buffers of a plurality of buffers for the first clock cycle to perform the write process, according to the updated second entry.

13. The controller of claim 11 , wherein the instructions when executed further cause the controller to set the third register to indicate a third entry subsequent to the second entry, in response to updating the second entry.

14. The controller of claim 11 , wherein the instructions when executed further cause the controller to determine whether to block updating the first register for a second clock cycle subsequent to the first clock cycle according to the second register and the third register.

15. The controller of claim 11 , wherein the instructions when executed further cause the controller to:

compare the first entry indicated by the second register and the second entry indicated by the third register, and

determine whether to block updating the first register for the first clock cycle according to the comparison.

16. The controller of claim 15 , wherein the instructions when executed further cause the controller to:

determine to block updating the first register for the first clock cycle, in response to the first entry indicated by the second register being equal to the second entry indicated by the third register, and

determine to unblock updating the first register for the first clock cycle, in response to the first entry indicated by the second register and the second entry indicated by the third register being different.

17. The controller of claim 11 , wherein the instructions when executed further cause the controller to:

clear the first entry, in response to receiving, from the memory bank, a write complete signal indicating that the write process on the memory bank has completed, and

set the second register to indicate a third entry subsequent to the first entry, in response to clearing the first entry.

18. An integrated circuit comprising:

a first register to store an address of a corresponding one of a plurality of memory banks;

a second register indicating a first entry storing an address of a memory bank, on which a write process is predicted to be completed next among the plurality of memory banks;

a third register indicating a second entry to be updated; and

a controller to:

update, for a first clock cycle, the second entry according to an input address of a target memory bank of the plurality of memory banks to store input data through the write process,

set the third register to indicate a third entry subsequent to the second entry, in response to updating the second entry, and

configure, for the first clock cycle, one or more buffers of a plurality of buffers to perform the write process, according to the updated second entry.

19. The integrated circuit of claim 18 , wherein the controller is to:

compare the first entry indicated by the second register and the third entry indicated by the third register to determine whether to block updating the first register for a second clock cycle subsequent to the first clock cycle; and

determine to block updating the first register for the second clock cycle, in response to the first entry indicated by the second register being equal to the third entry indicated by the third register.

20. The integrated circuit of claim 18 , wherein the controller is to:

determine to unblock updating the first register for the second clock cycle, in response to the first entry indicated by the second register and the third entry indicated by the third register being different.