Integrated circuit device

1. An integrated circuit (IC) device, comprising:

at least one delay circuit comprising:

an input and an output, and

a plurality of transistors electrically coupled with each other between the input and the output, the plurality of transistors configured to delay an input signal received at the input to generate a delayed signal at the output; and

an output connector electrically coupled to the output,

wherein

the output is in a first metal layer, and

the output connector comprises

a first conductive pattern in the first metal layer, and

a second conductive pattern in a second metal layer different from the first metal layer, the second conductive pattern electrically coupling the output to the first conductive pattern.

2. The IC device of claim 1 , wherein

the input is in the first metal layer.

3. The IC device of claim 1 , wherein

the plurality of transistors comprises at least one first transistor of a first type, and at least one second transistor of a second type different from the first type,

the delay circuit further comprises an extended contact structure over and in electrical contact with both a source/drain of the first transistor and a source/drain of the second transistor, and

the second conductive pattern overlapping the extended contact structure.

4. The IC device of claim 3 , wherein

the output overlaps the source/drain of one of the first transistor or the second transistor, and

the second conductive pattern overlaps

the source/drain of the other of the first transistor and the second transistor, or

an intermediate region between the source/drain of the first transistor and the source/drain of the second transistor.

5. The IC device of claim 1 , wherein

the at least one delay circuit comprises a plurality of delay circuits electrically coupled in series, with an output of a preceding delay circuit among the plurality of delay circuits being electrically coupled to an input of a succeeding delay circuit among the plurality of delay circuits.

6. The IC device of claim 1 , wherein

the plurality of transistors comprises first and second transistors of a first type, and third and fourth transistors of a second type different from the first type,

gates of the first through fourth transistors are electrically coupled to the input,

the first and third transistors are electrically coupled in series between a first node of a first power supply voltage and a second node of a second power supply voltage,

a source/drain of the first transistor and a source/drain of the third transistor are electrically coupled to a third node, and

the second and fourth transistors are electrically coupled in parallel between the third node and the output.

7. The IC device of claim 6 , wherein

the plurality of transistors further comprises at least one fifth transistor electrically coupled in series with the first and third transistors between the first node and the second node, and

a gate of the at least one fifth transistor is electrically coupled to the input.

8. The IC device of claim 1 , further comprising:

a first active region of a first semiconductor type, wherein

the first active region extends discontinuously along a first axis, and

the first active region comprises first and second portions spaced from each other along the first axis;

a second active region of a second semiconductor type different from the first semiconductor type, wherein

the second active region extends continuously along the first axis, and

the second active region overlaps, along a second axis transverse to the first axis, the first and second portions of the first active region and a spacing between the first and second portions of the first active region; and

first through third gate electrodes extending along the second axis and over the second active region, wherein

the first gate electrode is over the first portion of the first active region,

the second gate electrode is over the second portion of the first active region, and

the third gate electrode is over the spacing between the first and second portions of the first active region,

wherein

the plurality of transistors comprises

first and second transistors of a first type, and

third through fifth transistors of a second type different from the first type,

the first gate electrode and the first portion of the first active region are configured as the first transistor,

the second gate electrode and the second portion of the first active region are configured as the second transistor, and

the first through third gate electrodes and the second active region are correspondingly configured as the third through fifth transistors.

9. The IC device of claim 8 , further comprising:

a dummy gate electrode extending along the second axis, over the second active region and over the spacing between the first and second portions of the first active region.

10. The IC device of claim 1 , wherein

the plurality of transistors comprises a first transistor,

the delay circuit further comprises a plurality of via structures over and in electrical contact with a gate electrode of the first transistor, and

the plurality of via structures comprises at least one via structure which is free of direct electrical contact with a conductive element other than the gate electrode.

11. An integrated circuit (IC) device, comprising:

a first active region of a first semiconductor type, wherein

the first active region extends discontinuously along a first axis, and

the first active region comprises first and second portions spaced from each other along the first axis;

a second active region of a second semiconductor type different from the first semiconductor type, wherein

the second active region extends continuously along the first axis, and

the second active region overlaps, along a second axis transverse to the first axis, the first and second portions of the first active region and a spacing between the first and second portions of the first active region; and

a plurality of gate electrodes extending along the second axis and across the first and second active regions,

wherein

the plurality of gate electrodes and the first and second portions of the first active region are configured as a plurality of transistors of a first type,

the plurality of gate electrodes and the second active region are configured as a plurality of transistors of a second type different from the first type, and

the plurality of transistors of the first type and the plurality of transistors of the second type are electrically coupled into at least one delay circuit configured to delay an input signal at an input to generate a delayed signal at an output.

12. The IC device of claim 11 , wherein

the plurality of gate electrodes comprises first through third gate electrodes extending along the second axis and over the second active region, wherein

the first gate electrode is over the first portion of the first active region,

the second gate electrode is over the second portion of the first active region, and

the third gate electrode is over the spacing between the first and second portions of the first active region,

wherein

the delay circuit comprises

first and second transistors of the first type among the plurality of transistors of the first type, and

third through fifth transistors of the second type among the plurality of transistors of the second type,

the first gate electrode and the first portion of the first active region are configured as the first transistor,

the second gate electrode and the second portion of the first active region are configured as the second transistor, and

the first through third gate electrodes and the second active region are correspondingly configured as the third through fifth transistors.

13. The IC device of claim 12 , wherein

the plurality of gate electrodes further comprises a dummy gate electrode extending along the second axis, over the second active region and over the spacing between the first and second portions of the first active region.

14. The IC device of claim 11 , wherein

the first active region further comprises

a third portion opposite the first portion along the first axis, and

a plurality of second portions including the second portion,

the plurality of second portions are arranged along the first axis between the first and third portions,

the plurality of second portions are spaced from each other and from the first and third portions by a plurality of spacings including the spacing between the first and second portions, and

the second active region extends continuously along the first axis to overlap, along the second axis, the first portion, the plurality of second portions, the third portion, and the plurality of spacings.

15. The IC device of claim 14 , wherein

the at least one delay circuit comprises a plurality of delay circuits electrically coupled in series, with an output of a preceding delay circuit among the plurality of delay circuits being electrically coupled to an input of a succeeding delay circuit among the plurality of delay circuits.

16. The IC device of claim 14 , wherein, along the first axis,

a first length of each of the first and third portions is greater than a second length of each of the plurality of second portions, and

the second length of each of the plurality of second portions is greater than a third length of each of the plurality of spacings.

17. The IC device of claim 11 , further comprising:

a plurality of via structures over and in electrical contact with a gate electrode among the plurality of gate electrodes,

wherein the plurality of via structures comprises at least one via structure which is free of direct electrical contact with a conductive element other than the gate electrode.

18. An integrated circuit (IC) device, comprising:

a first active region of a first semiconductor type and extending along a first axis;

a second active region of a second semiconductor type different from the first semiconductor type, and extending along the first axis; and

a plurality of gate electrodes extending along a second axis transverse to the first axis, and across the first and second active regions,

wherein

the plurality of gate electrodes and the first active region are configured as a plurality of transistors of a first type,

the plurality of gate electrodes and the second active region are configured as a plurality of transistors of a second type different from the first type,

the plurality of transistors of the first type and the plurality of transistors of the second type are electrically coupled into at least one delay circuit configured to delay an input signal at an input to generate a delayed signal at an output,

the IC device further comprises, in or over the first active region, a structure configured to change a stress on the first active region to increase a threshold voltage of the plurality of transistors of the first type and increase a time delay of the at least one delay circuit.

19. The IC device of claim 18 , wherein

the structure comprises at least one via structure which is over and in electrical contact with a gate electrode among the plurality of gate electrodes, but is free of direct electrical contact with a conductive element other than the gate electrode, the at least one via structure over the first active region.

20. The IC device of claim 19 , further comprising:

a further via structure over and in electrical contact with the gate electrode, and electrically coupled to the input.