Display device and control method thereof

1. A display device, comprising:

a display panel, comprising a common electrode and a plurality of data lines; and

a voltage processing circuit, comprising a first input node electrically connected to the common electrode and a first output node electrically connected to at least one of the common electrode and the plurality of data lines,

wherein the voltage processing circuit is configured to obtain a common voltage signal of the common electrode in an nth frame through the first output node, and configured to control a voltage of the at least one of the common electrode and the plurality of data lines in an (n+k)th frame through the first output node in response to a difference between the common voltage signal of the nth frame and a standard voltage, where the n and k are positive integers;

wherein the voltage processing circuit comprises a voltage comparison circuit, which comprises a second input node electrically connected to the first input node, a second output node electrically connected to the first output node, and a third input node loaded with a frame synchronization signal, and the voltage comparison circuit is configured to generate a first target voltage signal in response to the difference between the common voltage signal in the nth frame and the standard voltage on a condition of a synchronization pulse occurring in the frame synchronization signal; and

wherein the voltage of the at least one of the common electrode and the plurality of data lines in the (n+k)th frame is related to the first target voltage signal.

2. The display device as claimed in claim 1 , wherein the voltage comparison circuit comprises:

a voltage comparator, comprising an input end electrically connected to the second input node and an output end;

a central controller, comprising a first sub-input end electrically connected to the third input node, a second sub-input end electrically connected to the output end of the first circuit, and a first sub-output end electrically connected to the second output node.

3. The display device as claimed in claim 1 , wherein the voltage comparison circuit comprises a digital-to-analog converter, and the digital-to-analog converter comprises a third sub-input end electrically connected to the third input node, a fourth sub-input end electrically connected to the second input node, and a second sub-output end electrically connected to the second output node.

4. The display device as claimed in claim 1 , wherein the voltage processing circuit further comprises a voltage superposition circuit;

the voltage superposition circuit comprises a fourth input node electrically connected to the second output node and a third output node electrically connected to the first output node;

the voltage superposition circuit is configured to obtain the first target voltage signal through the fourth input node, and generate a second target voltage signal in response to the first target voltage signal and in response to a to-be-superimposed voltage signal, and the voltage of the at least one of the common electrode and the plurality of data lines in the (n+k)th frame is related to the second target voltage signal; and

the to-be-superimposed voltage signal is related to at least one of the common voltage signal of the common electrode in the nth frame and data voltage signals of the plurality of data lines in the nth frame.

5. The display device as claimed in claim 4 , wherein the to-be-superimposed voltage signal is same as the common voltage signal of the common electrode in the nth frame.

6. The display device as claimed in claim 4 , wherein the to-be-superimposed voltage signal is related to a gamma voltage group corresponding to data voltages of the plurality of data lines in the nth frame.

7. The display device as claimed in claim 4 , wherein the voltage superposition circuit further comprises a fifth input node loaded with the to-be-superimposed voltage signal; and

the voltage superposition circuit comprises an adder or a subtracter, and the adder or the subtracter comprises a fifth sub-input end configured as the fourth input node, a sixth sub-input end configured as the fifth input node, and a third sub-output end configured as the third output node.

8. The display device as claimed in claim 1 , wherein the display device further comprises a data driving circuit, which comprises an input end is electrically connected to the first output node and an output end electrically connected to the plurality of data lines, and the data driving circuit is configured to control voltages of the plurality of data lines in the (n+k)th frame in response to the first target voltage signal.

9. The display device as claimed in claim 1 , wherein the display device further comprises a common driving circuit, which comprises an input end electrically connected to the first output node and an output end electrically connected to the common electrode, and the common driving circuit is configured to control the voltage of the common electrode in the (n+k)th frame in response to the first target voltage signal.

10. The display device as claimed in claim 1 , wherein the frame synchronization signal comprises a plurality of synchronization pulses, and each of the synchronization pulses indicates a starting of a corresponding frame.

11. The display device as claimed in claim 1 , wherein a displayed image of the display panel in the nth frame is at least partially same as a displayed image in the (n+k)th frame.

12. A control method of a display device, comprising steps of:

acquiring, by a voltage processing circuit, a common voltage signal of a common electrode in an nth frame;

acquiring, by a voltage comparison circuit of the voltage processing circuit, a frame synchronization signal; and

controlling a voltage of at least one of the common electrode and a plurality of data lines in an (n+k)th frame in response to a difference between the common voltage signal of the nth frame and a standard voltage signal on a condition of a synchronization pulse occurring in the frame synchronization signal, where the both n and k are positive integers.

13. The control method of the display device as claimed in claim 12 , wherein the step of controlling the voltage of the at least one of the common electrode and the plurality of data lines in the (n+k)th frame comprises:

generating, by voltage comparison circuit, a first target voltage signal in response to difference between the common voltage signal in the nth frame and the standard voltage signal on the condition of the synchronization pulse occurring in the frame synchronization signal; and

generating, by a voltage superposition circuit of the voltage processing circuit, a second target voltage signal in response to the first target voltage signal and in response to a to-be-superimposed voltage signal, and the voltage of the at least one of the common electrode and the plurality of data lines in the (n+k)th frame is related to the second target voltage signal.

14. A display device, comprising:

a display panel, comprising a common electrode and a plurality of data lines; and

a voltage processing circuit, comprising a first input node electrically connected to the common electrode and a first output node electrically connected to at least one of the common electrode and the plurality of data lines, and configured to obtain a common voltage signal of the common electrode in an nth frame through the first output node,

wherein the voltage processing circuit comprises a voltage comparison circuit, which comprises a second input node electrically connected to the first input node, a second output node electrically connected to the first output node, and a third input node loaded with a frame synchronization signal; and

wherein the voltage processing circuit is further configured to control a voltage of the at least one of the common electrode and the plurality of data lines in an (n+k)th frame through the first output node in response to a difference between the common voltage signal of the nth frame and a standard voltage on a condition of a synchronization pulse occurring in the frame synchronization signal, where n and k are positive integers.