CFET SRAM cell utilizing 8 transistors

1. A memory cell, comprising:

a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node;

a first complementary transmission gate including a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line;

a second complementary transmission gate including a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line;

a first word line connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates; and

a second word line connected to gate conductors of the first and second pMOS pass gates in the first and second complementary transmission gates,

wherein a signal drop is triggered on the second word line to generate a first voltage drop on the first bit line,

wherein, after the signal drop is triggered on the second word line, a bump voltage is generated at the first node and then the bump voltage drops, and

wherein a signal rise is triggered on the first word line, after the bump voltage drops, to generate a second voltage drop on the first bit line.

2. The memory cell of claim 1 , wherein the pair of cross-coupled inverters, the first complementary transmission gate, and the second complementary transmission gate are implemented within a single CFET cell.

3. The memory cell of claim 2 , wherein the CFET cell comprises a multilayer stacked structure, including:

a first metal layer, in which the first word line is disposed,

a first transistor layer,

a second transistor layer, and

a second metal layer, in which the second word line is disposed.

4. The memory cell of claim 3 , wherein the first transistor layer includes:

the first nMOS pass gate of the first complementary transmission gate,

the second nMOS pass gate of the second complementary transmission gate,

a first nMOS pull down transistor of a first one of the pair of cross-coupled inverters, and

a second nMOS pull down transistor of a second one of the pair of cross-coupled inverters.

5. The memory cell of claim 3 , wherein the first pMOS pass gate is disposed in the second transistor layer beneath the first nMOS pass gate disposed in the first transistor layer, and the second pMOS pass gate is disposed in the second transistor layer beneath the second nMOS pass gate disposed in the first transistor layer.

6. The memory cell of claim 3 , wherein the CFET cell further comprises:

a third metal layer, in which a set of complementary bit lines, and a power line VSS are disposed.

7. The memory cell of claim 3 , further comprising a buried power rail (BPR) used to write to a second word line.

8. A method for reading a memory cell, the memory cell comprising,

a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node;

a first complementary transmission gate including a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line;

a second complementary transmission gate including a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line;

a first word line connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates; and

a second word line connected to gate conductors of the first and second pMOS pass gates in the first and second complementary transmission gates,

the method comprising:

first triggering a signal drop on the second word line to generate a first voltage drop on the first bit line;

after the first triggering, waiting until a bump voltage at the first node drops; and

triggering a signal rise on the first word line after the bump voltage at the first node drops, to generate a second voltage drop on the first bit line.

9. The method of claim 8 , further including: synchronizing the first and second word lines to achieve a preferred read current, by initiating read of a weaker cell employing word line underdrive as a stability assist, whereby the first and second word lines are swept up to an operating voltage less than Vdd, allowing the bump voltage to discharge.