Displays with reduced data line crosstalk
A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.
1. A display, comprising:
display pixels configured to display an image; and
a data line configured to provide data signals to at least some of the display pixels, wherein at least one of the display pixels comprises:
a light-emitting diode;
drive transistor circuitry coupled in series with the light-emitting diode; and
a data loading transistor having a source region and a drain region, wherein
the source region is coupled to the drive transistor circuitry,
the data line is coupled to and routed over the drain region, and
the data line and the source region are non-overlapping to reduce crosstalk.
2. The display of claim 1 , wherein the at least one of the display pixels further comprises:
a semiconducting-oxide transistor coupled across the drain region and a gate of the drive transistor circuitry, wherein the drive transistor circuitry and the data loading transistor are silicon transistors;
a storage capacitor directly coupled to the gate of the drive transistor circuitry; and
a plurality of emission control transistors coupled in series with the light-emitting diode and the drive transistor circuitry.
3. The display of claim 1 , wherein:
the data loading transistor has a channel region that extends along a first direction;
the drive transistor circuitry has a first channel region and a second channel region separate from the first channel region; and
first and second channel regions extend along a second direction perpendicular to the first direction.
4. The display of claim 1 , wherein the drive transistor circuitry comprises:
a silicon trace forming a first drive transistor portion and a second drive transistor portion, wherein the first and second drive transistor portions are connected in series.
5. The display of claim 4 , wherein the drive transistor circuitry further comprises:
a gate conductor overlapping with the first drive transistor portion and the second drive transistor portion, wherein
a first portion of the silicon trace that is overlapped by the gate conductor comprises a first channel region of the first drive transistor portion, and
a second portion of the silicon trace that is overlapped by the gate conductor comprises a second channel region of the second drive transistor portion.
6. The display of claim 5 , wherein the first channel region is parallel to the second channel region.
7. The display of claim 5 , wherein
a third portion of the silicon trace connects the first channel region to the second channel region, and
the third portion of the silicon trace and the gate conductor are non-overlapping.
8. The display of claim 7 , wherein the third portion of the silicon trace has at least two bends.
9. The display of claim 8 , wherein the third portion of the silicon trace comprises:
a first segment parallel to the first channel region;
a second segment parallel to the second channel region; and
a third segment connecting the first segment to the second segment, wherein the third segment is perpendicular to the first and second segments.
10. The display of claim 5 , wherein
the first channel region has a width and a length, and
the length is at least two times longer than the width.
11. The display of claim 1 , wherein the at least one of the display pixels further comprises:
a metal shielding layer at least partially covering the data loading transistor.
12. The display of claim 11 , wherein the metal shielding layer is configured to receive a power supply voltage.
13. The display of claim 1 , wherein the at least one of the display pixels further comprises:
a metal shielding layer covering the drive transistor circuitry, wherein the metal shielding layer is configured to shield the drive transistor circuitry from parasitic coupling.
14. The display of claim 13 , wherein the metal shielding layer is biased to a power supply voltage level.
15. Display pixel circuitry comprising:
a light-emitting diode;
a data loading transistor having a drain region, a source region, and a channel region, wherein the channel region extends along a first direction between the drain and source regions;
drive transistor circuitry having first and second separate channel regions extending along a second direction different than the first direction; and
a data line coupled to the drain region without routing over the source region to reduce row-to-row crosstalk.
16. The display pixel circuitry of claim 15 , wherein the second direction is perpendicular to the first direction.
17. The display pixel circuitry of claim 15 , wherein the first and second separate channel regions are connected by a silicon trace portion having multiple bends.
18. The display pixel circuitry of claim 17 , wherein the drive transistor circuitry further comprises:
a gate conductor overlapping with the first and second separate channel regions, wherein the gate conductor and the silicon trace portion are non-overlapping.
19. The display pixel circuitry of claim 15 , further comprising:
a metal layer covering the drive transistor circuitry, wherein
the metal layer is configured to shield the drive transistor circuitry from parasitic coupling, and
the metal layer is configured to receive a positive power supply voltage.
20. An electronic device comprising:
control circuitry; and
a display configured to receive control signals from the control circuitry, wherein the display comprises:
an array of pixels; and
data lines coupled to respective columns of pixels in the array, wherein each pixel in the array comprises:
an organic light-emitting diode;
silicon drive transistor circuitry with at least two separate channel regions, wherein the silicon drive transistor circuitry has a gate terminal and a drain terminal;
a semiconducting-oxide transistor connected across the gate and drain terminals of the silicon drive transistor circuitry; and
a silicon data loading transistor configured to receive data signals from at least one of the data lines, wherein
the silicon data loading transistor has a source region and a drain region, and
the at least one of the data lines is coupled to the drain region without being routed over the source region.