Semiconductor structure having air gaps and method for manufacturing the same

1. A method for manufacturing a semiconductor structure, comprising:

preparing a dielectric structure which is formed with trenches respectively defined by lateral surfaces of the dielectric structure;

forming spacer layers on the lateral surfaces of the dielectric structure;

filling an electrically conductive material into the trenches to form electrically conductive features;

selectively depositing a blocking layer on the dielectric structure in such a manner that the electrically conductive features are exposed from the blocking layer;

selectively depositing a dielectric material on the exposed electrically conductive features to form a capping layer such that the electrically conductive features are covered by the capping layer and the spacer layers;

removing the blocking layer and the dielectric structure to form a plurality of recesses defined by the spacer layers;

filling a sacrificial material into the recesses so as to form sacrificial features;

forming a sustaining layer to cover the sacrificial features; and

removing the sacrificial features to form air gaps confined by the sustaining layer and the spacer layers.

2. The method according to claim 1 , wherein forming the spacer layers includes:

conformally forming a dielectric deposition layer on the dielectric structure; and

anisotropically etching the dielectric deposition layer to form the spacer layers.

3. The method according to claim 1 , wherein forming the sacrificial features includes:

filling the sacrificial material into the recesses; and

anisotropically etching the sacrificial material until the sacrificial features each having a predetermined height less than a height of each of the electrically conductive features are formed in the recesses.

4. The method according to claim 1 , wherein forming the sacrificial features includes:

filling the sacrificial material into the recesses such that a cap layer made of the sacrificial material is formed to fill the recesses and to cover the capping layer and the spacer layers; and

removing the capping layer and the cap layer to form the sacrificial features having top surfaces substantially horizontally flush with those of the electrically conductive features and the spacer layers.

5. The method according to claim 1 , wherein the sacrificial features are removed by a treatment selected from a thermal treatment, an ultraviolet treatment, or a combination thereof.

6. The method according to claim 5 , wherein the sacrificial features are removed by the thermal treatment at a temperature ranging from 300° C. to 400° C.

7. The method according to claim 5 , wherein the sacrificial features are removed by the ultraviolet treatment at an ultraviolet exposure energy density ranging from 10 mJ/cm 2 to 100 J/cm 2 .

8. The method according to claim 1 , wherein the sacrificial material is selected from polyurea, polylactic acid, polycaprolactone, poly(methyl methacrylate), poly(ethylene oxide), or combinations thereof.

9. The method according to claim 1 , further comprising, before selectively depositing the blocking layer, planarizing the electrically conductive features so as to permit a patterned dielectric layer of the dielectric structure to be exposed.

10. The method according to claim 9 , wherein the blocking layer is selectively deposited on the patterned dielectric layer of the dielectric structure.

11. The method according to claim 10 , wherein the blocking layer is made of a compound including a head group which contains silicon or carbon and which is used as an anchor to be bonded to a surface of the patterned dielectric layer.

12. The method according to claim 11 , wherein the compound is selected from butyltriethoxysilane, cyclohexyltrimethoxysilane, cyclopentyltrimethoxysilane, dodecyltriethoxysilane, dodecyltrimethoxysilane, decyltriethoxysilane, dimethoxy(methyl)-n-octylsilane, triethoxyethylsilane, ethyltrimethoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, hexadecyltrimethoxysilane, hexadecyltriethoxysilane, triethoxymethylsilane, trimethoxy(methyl)silane, methoxy(dimethyl)octadecylsilane, methoxy(dimethyl)-n-octylsilane, octadecyltriethoxysilane, triethoxy-n-octylsilane, octadecyltrimethoxysilane, trimethoxy(propyl)silane, trimethoxy-n-octylsilane, triethoxy(propyl)silane, methane, ethane, propane, butane, pentane, hexane, heptane, octane, nonane, decane, undecane, dodecane, pentadecane, hexadecane, or combinations thereof.

13. The method according to claim 1 , wherein the sustaining layer is porous.

14. The method according to claim 1 , wherein the sustaining layer is made of a porous silicon-based material selected from silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof.

15. A method for manufacturing a semiconductor structure, comprising:

forming an interconnect layer on a substrate;

forming a plurality of trenches on a dielectric structure disposed on the interconnect, the trenches being respectively defined by lateral surfaces of the dielectric structure;

forming spacer layers on the lateral surfaces of the dielectric structure;

filling an electrically conductive material into the trenches to form electrically conductive features;

selectively depositing a blocking layer on the dielectric structure in such a manner that the electrically conductive features are exposed from the blocking layer;

selectively depositing a dielectric material on the exposed electrically conductive features to form a capping layer such that the electrically conductive features are covered by the capping layer and the spacer layers;

removing the blocking layer and the dielectric structure to form a plurality of recesses defined by the spacer layers;

filling a sacrificial material into the recesses so as to form sacrificial features;

forming a porous sustaining layer covering the sacrificial features; and

removing the sacrificial features to form air gaps confined by the sustaining layer and the spacer layers.

16. The method according to claim 15 , further comprising, before selectively depositing the blocking layer, planarizing the electrically conductive features to permit a patterned dielectric layer of the dielectric structure to be exposed such that the blocking layer is selectively deposited on the patterned dielectric layer.

17. The method according to claim 16 , wherein the blocking layer is made of a compound including a head group which contains silicon or carbon and which is used as an anchor to be bonded to a surface of the patterned dielectric layer.

18. A method for manufacturing a semiconductor structure, comprising:

preparing a dielectric structure on a substrate, the dielectric structure includes a patterned dielectric layer and is formed with trenches respectively defined by lateral surfaces of the dielectric structure;

forming spacer layers on the lateral surfaces of the dielectric structure;

filling an electrically conductive material into the trenches to form electrically conductive features;

selectively depositing a blocking layer on the dielectric structure in such a manner that the electrically conductive features are exposed from the blocking layer;

selectively depositing a dielectric material on the exposed electrically conductive features to form a capping layer such that the electrically conductive features are covered by the capping layer and the spacer layers; and

removing the blocking layer and the dielectric structure to form a plurality of recesses defined by the spacer layers.

19. The method according to claim 18 , further comprising:

filling a sacrificial material into the recesses so as to form sacrificial features;

forming a sustaining layer to cover the sacrificial features; and

removing the sacrificial features to form air gaps confined by the sustaining layer and the spacer layers.

20. The method according to claim 19 , wherein the sustaining layer is porous.