Integrated circuit comprising a single photon avalanche diode and corresponding manufacturing method
A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.
1. An integrated circuit, comprising:
a semiconductor well doped with a first type of dopant; and
a single photon avalanche diode (SPAD) in the semiconductor well, said SPAD including a PN junction between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant;
wherein the first region comprises:
a first sub-region positioned in contact with a bottom of the second region and centered with respect to the second region;
a second sub-region forming an annular volume laterally surrounding the first sub-region and separated from the first sub-region at a gap by a portion of said semiconductor well; and
a third sub-region that diametrically connects opposite portions of the annular volume for the second sub-region and is in contact with a bottom of the first sub-region.
2. The integrated circuit according to claim 1 , wherein the second region is located at a surface of the semiconductor well at a position centered in a photosensitive area of the SPAD.
3. The integrated circuit according to claim 2 , wherein said gap has a lower concentration of dopants than in the first sub-region and the second sub-region.
4. The integrated circuit according to claim 3 , wherein a portion of the third sub-region locally passes through said gap.
5. The integrated circuit according to claim 1 , wherein the second sub-region and third sub-region have a same dopant concentration and same depth in the semiconductor substrate.
6. The integrated circuit according to claim 5 , wherein a dopant concentration of the first sub-region is less than the same dopant concentration of the second sub-region and third sub-region.
7. An integrated circuit, comprising:
a semiconductor well doped with a first type of dopant; and
a single photon avalanche diode (SPAD) in the semiconductor well, said SPAD including a PN junction between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant;
wherein the first region comprises:
a first sub-region positioned in contact with a bottom of the second region and centered with respect to the second region;
a second sub-region forming an annular volume laterally surrounding the first sub-region and an in contact with at least a side edge of the first sub-region; and
a third sub-region that diametrically connects opposite portions of the annular volume for the second sub-region and is in contact with a bottom of the first sub-region.
8. The integrated circuit according to claim 7 , wherein the second region is located at a surface of the semiconductor well at a position centered in a photosensitive area of the SPAD.
9. The integrated circuit according to claim 7 , wherein the second sub-region and third sub-region have a same dopant concentration and same depth in the semiconductor substrate.
10. The integrated circuit according to claim 9 , wherein a dopant concentration of the first sub-region is less than the same dopant concentration of the second sub-region and third sub-region.
11. An integrated circuit, comprising:
a semiconductor well doped with a first type of dopant; and
a single photon avalanche diode (SPAD) in the semiconductor well, said SPAD including a PN junction between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant;
wherein the first region comprises:
a first sub-region positioned in contact with a bottom of the second region and centered with respect to the second region;
a second sub-region forming an annular volume laterally surrounding the first sub-region and an in contact with at least a side edge of the first sub-region; and
a third sub-region that is laterally isolated from the second sub-region and positioned in contact with a bottom of the first sub-region.
12. The integrated circuit according to claim 11 , wherein the third sub-region is centered with respect to the annular volume of the second sub-region.
13. The integrated circuit according to claim 11 , wherein the second region is located at a surface of the semiconductor well at a position centered in a photosensitive area of the SPAD.
14. The integrated circuit according to claim 11 , wherein the second sub-region and third sub-region have a same dopant concentration and same depth in the semiconductor substrate.
15. The integrated circuit according to claim 14 , wherein a dopant concentration of the first sub-region is less than the same dopant concentration of the second sub-region and third sub-region.
16. An integrated circuit, comprising:
a semiconductor well doped with a first type of dopant; and
a single photon avalanche diode (SPAD) in the semiconductor well, said SPAD including a PN junction between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant;
wherein the first region comprises:
a first sub-region positioned in contact with a bottom of the second region and centered with respect to the second region;
a second sub-region forming an annular volume laterally surrounding the first sub-region and an in contact with at least a side edge of the first sub-region; and
a plurality of third sub-regions where each third region radially extends inwardly from the annular volume of the second sub-region and is in contact with a bottom of the first sub-region.
17. The integrated circuit according to claim 16 , wherein the second region is located at a surface of the semiconductor well at a position centered in a photosensitive area of the SPAD.
18. The integrated circuit according to claim 16 , wherein the second sub-region and third sub-region have a same dopant concentration and same depth in the semiconductor substrate.
19. The integrated circuit according to claim 18 , wherein a dopant concentration of the first sub-region is less than the same dopant concentration of the second sub-region and third sub-region.