Integrated artificial neuron device
An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.
1. An integrated artificial neuron device, comprising:
an integrator circuit coupled between an input node at which at least one input signal is received and an output node at which the integrator circuit delivers at least one output signal; and
a refractory circuit configured to inhibit the integrator circuit for an inhibition duration after the delivery of the at least one output signal, the refractory circuit comprising:
a first transistor having a first conduction terminal coupled to a supply node, a second conduction terminal coupled to a common node, and a control terminal coupled to the output node;
a second transistor having a first conduction terminal coupled to the input node, a second conduction terminal coupled to a reference node at which a reference voltage is received, and a control terminal coupled to the common node; and
a resistive-capacitive circuit comprising a capacitor coupled between the supply node and the common node and a resistor coupled between the common node and the reference node, wherein the inhibition duration is dependent upon a time constant of the resistive-capacitive circuit.
2. The integrated artificial neuron device of claim 1 , wherein the capacitor is directly electrically connected between the supply node and the common node, and the resistor is directly electrically connected between the common node and the reference node.
3. The integrated artificial neuron device of claim 1 , wherein the capacitor comprises a MOS transistor configured for use as a capacitor.
4. The integrated artificial neuron device of claim 3 , wherein the MOS transistor of the capacitor has a surface area of one square micrometer.
5. The integrated artificial neuron device of claim 1 , wherein the resistor comprises a MOS transistor configured for use as a resistor.
6. The integrated artificial neuron device of claim 1 , wherein the resistor has a resistance of one giga-ohm.
7. An integrated artificial neuron device, comprising:
an integrator circuit coupled between an input node at which at least one input signal is received and an output node at which the integrator circuit delivers at least one output signal; and
a refractory circuit configured to inhibit the integrator circuit for an inhibition duration after the delivery of the at least one output signal, the refractory circuit comprising:
a first transistor comprising a first n-channel MOS transistor having a drain coupled to a supply node, a source coupled to a common node, and a gate coupled to the output node;
a second transistor comprising a second n-channel MOS transistor having a drain coupled to the input node, a source coupled to a reference node, and a gate coupled to the common node; and
a resistive-capacitive circuit coupled between the supply node and the reference node and having a tap coupled to the common node, wherein the inhibition duration is dependent upon a time constant of the resistive-capacitive circuit.
8. The integrated artificial neuron device of claim 7 , wherein the first transistor comprises a first n-channel MOS transistor having a drain directly electrically connected to the supply node, a source directly electrically connected to the common node, and a gate directly electrically connected to the output node; and wherein the second transistor comprises a second n-channel MOS transistor having a drain directly electrically connected to the input node, a source directly electrically connected to the reference node, and a gate directly electrically connected to the common node.
9. A refractory circuit configured to inhibit operation of an integrator circuit after delivery of an output signal, the refractory circuit comprising:
a first transistor having a first conduction terminal coupled to a supply node, a second conduction terminal coupled to a common node, and a control terminal coupled to an output node at which the output signal is delivered;
a second transistor having a first conduction terminal coupled to an input node, a second conduction terminal coupled to a reference node at which a reference voltage is received, and a control terminal coupled to the common node; and
a resistive-capacitive circuit comprising a capacitor coupled between the supply node and the common node and a resistor coupled between the common node and the reference node, wherein a duration of inhabitation of the integrated circuit by the refractory circuit is dependent upon a time constant of the resistive-capacitive circuit.
10. The refractory circuit of claim 9 , wherein the capacitor is directly electrically connected between the supply node and the common node, and the resistor is directly electrically connected between the common node and the reference node.
11. The refractory circuit of claim 9 , wherein the capacitor comprises a MOS transistor configured for use as a capacitor.
12. The refractory circuit of claim 11 , wherein the MOS transistor of the capacitor has a surface area of one square micrometer.
13. The refractory circuit of claim 9 , wherein the resistor comprises a MOS transistor configured for use as a resistor.
14. The refractory circuit of claim 13 , wherein the resistor has a resistance of one giga-ohm.
15. A refractory circuit configured to inhibit operation of an integrator circuit after delivery of an output signal, the refractory circuit comprising:
a first transistor comprising a first n-channel MOS transistor having a drain coupled to a supply node, a source coupled to a common node, and a gate coupled to an output node at which the output signal is delivered;
a second transistor comprising a second n-channel MOS transistor having a drain coupled to an input node, a source coupled to a reference node at which a reference voltage is received, and a gate coupled to the common node; and
a resistive-capacitive circuit coupled between the supply node and the reference node and having a tap coupled to the common node, wherein a duration of inhabitation of the integrator circuit by the refractory circuit is dependent upon a time constant of the resistive-capacitive circuit.
16. The refractory circuit of claim 15 , wherein the first transistor comprises a first n-channel MOS transistor having a drain directly electrically connected to the supply node, a source directly electrically connected to the common node, and a gate directly electrically connected to the output node; and wherein the second transistor comprises a second n-channel MOS transistor having a drain directly electrically connected to the input node, a source directly electrically connected to the reference node, and a gate directly electrically connected to the common node.
17. The integrated artificial neuron device of claim 7 , wherein the resistive-capacitive circuit comprises a capacitor directly electrically connected between the supply node and the common node, and a resistor directly electrically connected between the common node and the reference node.
18. The integrated artificial neuron device of claim 17 , wherein the capacitor comprises a MOS transistor configured for use as a capacitor.
19. The integrated artificial neuron device of claim 18 , wherein the MOS transistor of the capacitor has a surface area of one square micrometer.
20. The integrated artificial neuron device of claim 17 , wherein the resistor comprises a MOS transistor configured for use as a resistor.
21. The integrated artificial neuron device of claim 20 , wherein the resistor has a resistance of one giga-ohm.
22. The refractory circuit of claim 15 , wherein the resistive-capacitive circuit comprises a capacitor directly electrically connected between the supply node and the common node, and a resistor directly electrically connected between the common node and the reference node.
23. The refractory circuit of claim 22 , wherein the capacitor comprises a MOS transistor configured for use as a capacitor.
24. The refractory circuit of claim 23 , wherein the MOS transistor of the capacitor has a surface area of one square micrometer.
25. The refractory circuit of claim 22 , wherein the resistor comprises a MOS transistor configured for use as a resistor.
26. The refractory circuit of claim 25 , wherein the resistor has a resistance of one giga-ohm.