IP Library › Granted Patent US 11,960,739
Granted Patent B1
US 11,960,739 · App. 17/929,191 · Granted Apr 16, 2024

Nominal distance reference voltage calibration

Inventors: Robert E. Jeter (Santa Clara, CA); Jingkui Zheng (Sunnyvale, CA); David A. Knopf (San Jose, CA); Satish B. Dulam (Sunnyvale, CA); Kai Lun Hsiung (Fremont, CA); Venkata Ramana Malladi (Santa Clara, CA); Rahul Ranjan (Campbell, CA)
Assignee: Apple Inc.
G06F3/0632G06F3/0614G06F3/0658G06F3/0673G11C7/22G11C2207/2254
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Quick Facts
Patent No.
US 11,960,739
App. No.
17/929,191
Granted
Apr 16, 2024
Kind
B1
Abstract

The present disclosure is directed to a reference voltage calibration. An apparatus includes a memory and a memory controller including a calibration circuit configured to perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory. The reference voltage calibration comprises performing horizontal calibrations at different reference voltage values to determine a range of delay values applied to a data strobe signal at which valid data is read from the memory. The calibration includes determining scores corresponding to ones of the plurality of horizontal calibrations in which a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin. Thereafter, the calibration circuit selects a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.

Claims (46)

1. An apparatus comprising:

a memory; and

a memory controller coupled to the memory, wherein the memory controller includes a calibration circuit configured to:

perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory, wherein the reference voltage calibration comprises performing a plurality of horizontal calibrations at different reference voltage values, and wherein ones of the horizontal calibrations comprise determining a range of delay values applied to a data strobe signal at which valid data is read from the memory;

determine scores corresponding to ones of the plurality of horizontal calibrations, wherein a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin; and

select a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.

2. The apparatus of claim 1 , wherein, to determine a score for a particular horizontal calibration of the plurality of horizontal calibrations, the calibration circuit is configured to:

determine a preliminary score that is based on the range of delay values such that a greater range of delay values corresponds to a greater score; and

determine a penalty score that is based on a difference between a particular reference voltage value at which the horizontal calibration was conducted and a nominal reference voltage value;

wherein a score for the particular reference voltage value is calculated by subtracting the penalty score from the preliminary score.

3. The apparatus of claim 2 , wherein the penalty score is based on a value that is proportional to the difference between a particular reference voltage value at which the horizontal calibration was conducted and the nominal reference voltage value.

4. The apparatus of claim 2 , wherein the penalty score is based on an exponential value corresponding to the difference between a particular reference voltage value at which the horizontal calibration was conducted and the nominal reference voltage value.

5. The apparatus of claim 2 wherein the calibration circuit is configured to update the nominal reference voltage based on the calibrated reference voltage.

6. The apparatus of claim 2 , wherein the nominal reference voltage value is a static value.

7. The apparatus of claim 1 , wherein the calibration circuit is configured to select the calibrated reference voltage based on a particular reference voltage value for which a corresponding horizontal calibration yielded a highest score.

8. The apparatus of claim 1 , wherein the calibration circuit is further configured to, concurrent with performing the reference voltage calibration, initiate a background calibration by sending a first command to the memory.

9. The apparatus of claim 8 , wherein the memory includes a ring oscillator and a counters, and wherein performing the background calibration comprises the ring oscillator incrementing the counter in response to receiving the first command.

10. The apparatus of claim 9 , wherein the calibration circuit is further configured to:

send a second command to the memory to complete the background calibration, wherein the memory is configured to convey a count value to the calibration circuit in response to receiving the second command; and

adjust a write clock signal conveyed between the memory controller and the memory based on the count value.

11. A method comprising:

performing, using a calibration circuit, a plurality of horizontal calibrations at different reference voltage values to determine a calibrated reference voltage, wherein the reference voltage values are used to distinguish between logic values read from a memory by a memory controller, and wherein ones of the plurality of horizontal calibrations comprise determining a range of delay values applied to a data strobe signal at which valid data is read from the memory;

determining, using the calibration circuit, scores corresponding to ones of the plurality of horizontal calibrations, wherein a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin; and

selecting, using the calibration circuit, the calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.

12. The method of claim 11 , wherein the method further comprises:

determining, by the calibration circuit for a particular horizontal calibration of the plurality of horizontal calibrations, a preliminary score that is based on the range of delay values such that a greater range of delay values corresponds to a greater score; and

determining, by the calibration circuit, a penalty score that is based on a difference between a particular reference voltage value at which the horizontal calibration was conducted and a nominal reference voltage value;

wherein a score for the particular reference voltage value is calculated by subtracting the penalty score from the preliminary score.

13. The method of claim 12 , wherein the penalty score is based on a value that is proportional to the difference between a particular reference voltage value at which the horizontal calibration was conducted and the nominal reference voltage value.

14. The method of claim 12 , further comprising updating, by the calibration circuit, the nominal reference voltage based on the calibrated reference voltage.

15. The method of claim 11 , further comprising selecting, using the calibration circuit, the calibrated reference voltage based on a particular reference voltage value for which a corresponding one of the plurality of horizontal calibrations yielded a highest score.

16. The method of claim 11 , wherein the method further comprises:

concurrent with performing the plurality of horizontal calibrations, initiating, by the calibration circuit a background calibration by sending a first command to the memory, wherein performing the background calibration comprises a ring oscillator implemented on the memory incrementing a counter in response to the first command.

17. The method of claim 16 , further comprising:

sending, by the calibration circuit, a second command to the memory to complete the background calibration, wherein the memory is configured to convey a count value to the calibration circuit in response to receiving the second command; and

adjusting, by the calibration circuit, a write clock signal conveyed between the memory controller and the memory based on the count value.

18. A system comprising:

a memory subsystem including a memory coupled to a memory controller, wherein the memory controller includes a calibration circuit configured to perform reference voltage calibrations, wherein, in performing the reference voltage calibrations, the calibration circuit is configured to:

perform a plurality of horizontal calibrations at different reference voltage values, and wherein ones of the horizontal calibrations comprise determining a range of delay values applied to a data strobe signal at which valid data is read from the memory;

determine scores corresponding to ones of the plurality of horizontal calibrations, wherein a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin; and

select a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.

19. The system of claim 18 , wherein, to determine a score for a particular horizontal calibration of the plurality of horizontal calibrations, the calibration circuit is configured to:

determine a preliminary score that is based on the range of delay values such that a greater range of delay values corresponds to a greater score; and

determine a penalty score that is based on a difference between a particular reference voltage value at which the horizontal calibration was conducted and a nominal reference voltage value;

wherein a score for the particular reference voltage value is calculated by subtracting the penalty score from the preliminary score.

20. The system of claim 19 , wherein the penalty score is based on a value that is proportional to the difference between a particular reference voltage value at which the horizontal calibration was conducted and the nominal reference voltage value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2022
From: JETER, ROBERT E.; ZHENG, JINGKUI; KNOPF, DAVID A.; DULAM, SATISH B.; HSIUNG, KAI LUN; MALLADI, VENKATA RAMANA; RANJAN, RAHUL
To: APPLE INC.
Reel/Frame 060969/0744 →
Cited By (3)
US 12,288,583 US 12,327,612 US 12,367,915