Memory device and method for controlling row hammer
A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.
1. A memory device comprising:
a memory cell array including a plurality of memory cell rows;
a control logic circuit configured to monitor access addresses for the memory cell array to detect a first hammer address and a second hammer address; and
a refresh control circuit configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the first hammer address,
wherein the first hammer address includes a row hammer address of memory cell rows having the number of accesses equal to or more than a predetermined number of times or having a relatively higher number of accesses as compared with other access addresses during a first row hammer monitoring time frame,
wherein the second hammer address includes a malicious row hammer address of memory cell rows accessed at random sampling time points during a second row hammer monitoring time frame, and being the same as the row hammer address,
wherein the control logic circuit is configured to count the number of malicious row hammer addresses, and
wherein the refresh control circuit is configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address when the counted number of malicious row hammer addresses exceeds a threshold value.
2. The memory device of claim 1 , wherein the first and second row hammer monitoring time frames are set identically.
3. The memory device of claim 2 , wherein the control logic circuit is configured to use a refresh window tREFw set in the memory device as the first and second row hammer monitoring time frames.
4. The memory device of claim 1 , wherein the first row hammer monitoring time frame is longer than the second row hammer monitoring time frame.
5. The memory device of claim 1 , wherein the control logic circuit is configured to use a refresh time interval tREFi set in the memory device as the second row hammer monitoring time frame.
6. The memory device of claim 1 , wherein the control logic circuit is configured to use a refresh window tREFw set in the memory device as the first row hammer monitoring time frame.
7. The memory device of claim 1 , wherein the control logic circuit is configured to:
store first count values counting the number of accesses of addresses accessed during the first row hammer monitoring time frame,
among the first count values, select particular count values equal to or more than the predetermined number of times or relatively higher count values as compared with other the first count values, and
set an address corresponding to the selected particular count values or the relatively higher count values to the row hammer address.
8. The memory device of claim 7 , wherein the refresh control circuit is configured to generate a refresh address signal indicating an address of a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.
9. The memory device of claim 7 , wherein the control logic circuit is configured to reset the first count values after the first row hammer monitoring time frame elapses.
10. The memory device of claim 1 , wherein the control logic circuit includes:
a randomizer configured to provide the random sampling time points during the second row hammer monitoring time frame; and
a random sampling register configured to store addresses as a random sampling address accessed at the random sampling time points.
11. The memory device of claim 10 , wherein the randomizer includes a linear feedback shift register configured to output a plurality of bits and set the random sampling time points by using the output bits of the linear feedback shift register.
12. The memory device of claim 10 , wherein the control logic circuit includes:
a comparator configured to compare the random sampling address with the row hammer address, and output the row hammer address as the malicious row hammer address if the row hammer address is the same as the random sampling address based on a result of the comparison; and
a similarity counter circuit configured to store a second count value obtained by counting the number of malicious row hammer addresses and when the second count value exceeds the threshold value, provide the malicious row hammer address to an external device.
13. The memory device of claim 12 , wherein the refresh control circuit is configured to refresh the memory cell row physically adjacent to the memory cell row corresponding to the malicious row hammer address.
14. The memory device of claim 12 , wherein the control logic circuit is configured to inform the external device of information on the malicious row hammer address when the counted number of malicious row hammer addresses exceeds the threshold value.
15. The memory device of claim 12 , wherein the control logic circuit is configured to reset the second count value after the second row hammer monitoring time frame elapses.
16. A memory device comprising:
a memory cell array including a plurality of memory cell rows;
a control logic circuit configured to detect:
a row hammer address of memory cell rows having the number of accesses equal to or more than a predetermined number of times or having a relatively higher number of accesses as compared with other access addresses during a first row hammer monitoring time frame, and
a malicious row hammer address of memory cell rows accessed at random sampling time points during a second row hammer monitoring time frame, and being the same as the row hammer address; and
a refresh control circuit configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address,
wherein the control logic circuit comprises:
a first register configured to store random sampling addresses of memory cell rows accessed at the random sampling time points; and
a comparator configured to compare the row hammer address with the random sampling addresses, and output the row hammer address as the malicious row hammer address when one of the random sampling addresses is identical to the row hammer address based on a result of the comparison; and
a similarity counter circuit configured to count the number of malicious row hammer addresses, and
wherein the refresh control circuit is configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address when the counted number of malicious row hammer addresses exceeds a threshold value.
17. The memory device of claim 16 , wherein the control logic circuit further comprises a randomizer including a linear feedback shift register configured to output a plurality of bits and set the random sampling time points by using the output bits of the linear feedback shift register during the second row hammer monitoring time frame.
18. The memory device of claim 16 , wherein the control logic circuit further comprises:
a first counter configured to store first count values counting the number of accesses of addresses accessed during the first row hammer monitoring time frame; and
a second register configured to select, among the first count values, particular count values equal to or more than the predetermined number of times or relatively higher count values as compared with other the first count values, and store addresses corresponding to the selected particular count values or the relatively higher count values as the row hammer address.
19. A method of operating a memory device including a plurality of memory cell rows, the method comprising:
detecting a first hammer address and a second hammer address by monitoring the number of accesses of addresses for the memory cell rows;
storing the first hammer address as a row hammer address of memory cell rows having the number of accesses equal to or more than a predetermined number of times or having a relatively higher number of accesses as compared with other access addresses during a first row hammer monitoring time frame;
storing the second hammer address as a malicious row hammer address of memory cell rows accessed at random sampling time points during a second row hammer monitoring time frame, and being the same as the row hammer address;
counting the number of malicious row hammer addresses;
performing a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address; and
performing a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address when the counted number of malicious row hammer addresses exceeds a threshold value.
20. The method of claim 19 , further comprising:
storing first count values for counting the number of accesses of addresses accessed during the first row hammer monitoring time frame;
selecting particular count values equal to or more than the predetermined number of times or relatively higher count values as compared with other the first count values; and
providing an address corresponding to the selected particular count values or the relatively higher count values as the row hammer address.