IP Library Granted Patent US 11,967,463
Granted Patent B2
US 11,967,463 · App. 17/827,347 · Granted Apr 23, 2024

Ceramic electronic device

Inventor: Teruo Atsumi (Tokyo, JP)
Assignee: TAIYO YUDEN CO., LTD.
H01G4/012H01G4/30
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Quick Facts
Patent No.
US 11,967,463
App. No.
17/827,347
Granted
Apr 23, 2024
Kind
B2
Abstract

A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of a plurality of internal electrode layers having pores are alternately stacked. A continuity modulus of at least one of the plurality of internal electrode layers is 80% or less. An average pore diameter of the pores of the at least one of the plurality of internal electrode layers is equal to or less than each thickness of the plurality of dielectric layers.

Claims (15)

1. A ceramic electronic device comprising:

a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of a plurality of internal electrode layers having pores are alternately stacked,

wherein a continuity modulus of at least one of the plurality of internal electrode layers is 80% or less, and

wherein an average pore diameter of the pores of the at least one of the plurality of internal electrode layers is equal to or less than each thickness of the plurality of dielectric layers.

2. The ceramic electronic device as claimed in claim 1 , wherein the continuity modulus is 50% or more.

3. The ceramic electronic device as claimed in claim 1 wherein the average pore diameter is 100 μm or less.

4. The ceramic electronic device as claimed in claim 1 , wherein an average thickness of the plurality of dielectric layers is 0.1 μm or more and 10 μm or less.

5. The ceramic electronic device as claimed in claim 1 , wherein an average thickness of the plurality of internal electrode layers is 0.1 μm or more and 3 μm or less.

6. The ceramic electronic device as claimed in claim 1 ,

wherein the average pore diameter is defined as 4/π×ΣDm/m, when a number of the pores in an observation area of a cross section of one selected internal electrode layer of the plurality of internal electrode layers is “m”, and a total length of the pores is ΣDm.

7. The ceramic electronic device as claimed in claim 6 ,

wherein the average pore diameter is calculated by extracting pores having a length of 1/10 or more of an average thickness of the plurality of dielectric layers.

8. The ceramic electronic device as claimed in claim 1 ,

wherein each thickness of the plurality of dielectric layers is 1 μm or less, and

wherein the average pore diameter of the pores is 1 μm or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2022
From: ATSUMI, TERUO
To: TAIYO YUDEN CO., LTD.
Reel/Frame 060043/0015 →
Priority Claims (1)
JP 2021-104045 · Jun 23, 2021 · national
Continuity (1)
Related Publication 20220415574A1 · Dec 29, 2022