Electrostatic discharge protection circuit and semiconductor circuit

1. An ESD protection circuit, coupled between a first reference terminal and a second reference terminal, the electrostatic discharge protection circuit comprising:

a first voltage divider;

a second voltage divider;

a first trigger circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, the second terminal is coupled to the second reference terminal via the first voltage divider;

a second trigger circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection;

a first discharge component, comprising a gate, a first source/drain and a second source/drain, wherein the gate is coupled between the first trigger circuit and the first voltage divider, and the first source/drain of the first discharge component is coupled to the first voltage divider, wherein the first discharge component has a threshold voltage, and when a voltage of the gate of the first discharge component is higher than a voltage of the first source/drain or the second source/drain and a difference therebetween exceeds the threshold voltage of the first discharge component, the first discharge component conducts; and

a second discharge component, comprising a gate, a first source/drain and a second source/drain, wherein the gate is coupled between the second trigger circuit and the second voltage divider, and the first source/drain of the second discharge component is coupled to the second voltage divider, and the first discharge component and the second discharge component are in series connection,

wherein the first trigger circuit comprises a first GaN based transistor, comprising a first source/drain, a second source/drain and a gate, wherein the first source/drain and the second source/drain of the first GaN based transistor are coupled to the first terminal of the first trigger circuit, and the gate of the first GaN based transistor is coupled to the second terminal of the first trigger circuit.

2. The ESD protection circuit of claim 1 , wherein the second source/drain of the first discharge component is coupled to the second source/drain of the second discharge component.

3. The ESD protection circuit of claim 1 , wherein the first voltage divider comprises a first resistor, and the second voltage divider comprises a second resistor.

4. The ESD protection circuit of claim 1 , wherein the first discharge component comprises a second GaN based transistor, and the second discharge component comprises a third GaN based transistor.

5. The ESD protection circuit of claim 1 , wherein the first trigger circuit has a threshold voltage, and when a voltage of the first terminal of the first trigger circuit is higher than a voltage of the second terminal and a difference therebetween exceeds the threshold voltage of the first trigger circuit, the first trigger circuit conducts, and the threshold voltage of the first trigger circuit is greater than the threshold voltage of the first discharge component.

6. The ESD protection circuit of claim 1 , wherein the second trigger circuit has a threshold voltage, when a voltage of the first terminal of the second trigger circuit is higher than a voltage of the second terminal and a difference therebetween exceeds the threshold voltage of the second trigger circuit, the second trigger circuit conducts; and the second discharge component has a threshold voltage, and when a voltage of the gate of the second discharge component is higher than a voltage of the first source/drain or the second source/drain and a difference therebetween exceeds the threshold voltage of the second discharge component, the second discharge component conducts, and the threshold voltage of the second trigger circuit is greater than the threshold voltage of the second discharge component.

7. The ESD protection circuit of claim 1 , wherein the second trigger circuit comprises a fourth GaN based transistor, comprising a first source/drain, a second source/drain and a gate, wherein the first source/drain and the second source/drain of the fourth GaN based transistor are coupled to the first terminal of the second trigger circuit, and the gate of the fourth GaN based transistor is coupled to the second terminal of the second trigger circuit.

8. The ESD protection circuit of claim 1 , wherein the first trigger circuit comprises a plurality of GaN based transistors, wherein each GaN based transistor comprises a source, a drain and a gate, and the source of each GaN based transistor is coupled to the gate, and the plurality of GaN based transistors are in series connection.

9. An ESD protection circuit, coupled between a first reference terminal and a second reference terminal, the electrostatic discharge protection circuit comprising:

a first voltage divider;

a second voltage divider;

a first trigger circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, the second terminal is coupled to the second reference terminal via the first voltage divider;

a second trigger circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection;

a first discharge component, comprising a gate, a first source/drain and a second source/drain, wherein the gate is coupled between the first trigger circuit and the first voltage divider; and

a second discharge component, comprising a gate, a first source/drain and a second source/drain, wherein the gate is coupled between the second trigger circuit and the second voltage divider, and the first discharge component and the second are in series connection;

wherein the first trigger circuit comprises a third GaN based transistor comprising a first source/drain, a second source/drain and a gate, wherein the first source/drain and the second source/drain of the third GaN based transistor are coupled to the first terminal of the first trigger circuit, and the gate of the third GaN based transistor is coupled to the second terminal of the first trigger circuit.

10. The ESD protection circuit of claim 9 , wherein the first source/drain of the first discharge component is coupled to the first reference terminal, the first source/drain of the second discharge component is coupled to the second reference terminal, and the second source/drain of the first discharge component is coupled to the second source/drain of the second discharge component.

11. The ESD protection circuit of claim 9 , wherein the first voltage divider comprises a first resistor, and the second voltage divider comprises a second resistor.

12. The ESD protection circuit of claim 9 , wherein the first discharge component comprises a first GaN based transistor, and the second discharge component comprises a second GaN based transistor.

13. The ESD protection circuit of claim 9 , wherein the second trigger circuit comprises a fourth GaN based transistor, comprising a first source/drain, a second source/drain and a gate, wherein the first source/drain and the second source/drain of the fourth GaN based transistor are coupled to the first terminal of the second trigger circuit, and the gate of the fourth GaN based transistor is coupled to the second terminal of the second trigger circuit.

14. An ESD protection circuit, coupled between a first reference terminal and a second reference terminal, the electrostatic discharge protection circuit comprising:

a first voltage divider;

a second voltage divider;

a first trigger circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, the second terminal is coupled to the second reference terminal via the first voltage divider;

a second trigger circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection;

a first discharge component, comprising a first GaN based transistor, including a gate, a first source/drain and a second source/drain, wherein the gate of the first discharge component is coupled between the first trigger circuit and the first voltage divider; and

a second discharge component, comprising a gate, a first source/drain and a second source/drain, wherein the gate of the second discharge component is coupled between the second trigger circuit and the second voltage divider, and the first discharge component and the second are in series connection;

wherein the first trigger circuit comprises a plurality of GaN based transistors, wherein each GaN based transistor comprises a source, a drain and a gate, and the source of each GaN based transistor is coupled to the gate, and the plurality of GaN based transistors are in series connection,

wherein the first trigger circuit has a threshold voltage, and when a voltage of the first terminal of the first trigger circuit is higher than a voltage of the second terminal and a difference therebetween exceeds the threshold voltage of the first trigger circuit, the first trigger circuit conducts; and the first discharge component has a threshold voltage, and when a voltage of the gate of the first discharge component is higher than a voltage of the first source/drain or the second source/drain and a difference therebetween exceeds the threshold voltage of the first discharge component, the first discharge component conducts, and the threshold voltage of the first trigger circuit is greater than the threshold voltage of the first discharge component.

15. The ESD protection circuit of claim 14 , wherein the first source/drain of the first discharge component is coupled to the first reference terminal, the first source/drain of the second discharge component is coupled to the second reference terminal, and the second source/drain of the first discharge component is coupled to the second source/drain of the second discharge component.

16. The ESD protection circuit of claim 14 , wherein the first voltage divider comprises a first resistor, and the second voltage divider comprises a second resistor.

17. The ESD protection circuit of claim 14 , wherein the second discharge component comprises a second GaN based transistor.

18. The ESD protection circuit of claim 14 , wherein the second trigger circuit has a threshold voltage, when a voltage of the first terminal of the second trigger circuit is higher than a voltage of the second terminal and a difference therebetween exceeds the threshold voltage of the second trigger circuit, the second trigger circuit conducts; and the second discharge component has a threshold voltage, and when a voltage of the gate of the second discharge component is higher than a voltage of the first source/drain or the second source/drain and a difference therebetween exceeds the threshold voltage of the second discharge component, the second discharge component conducts, and the threshold voltage of the second trigger circuit is greater than the threshold voltage of the second discharge component.

19. The ESD protection circuit of claim 14 , wherein the second trigger circuit comprises a plurality of GaN based transistor, wherein each GaN based transistor comprises a source, a drain and a gate, and the source of each GaN based transistor is coupled to the gate, and the plurality of GaN based transistors are in series connection.

20. The ESD protection circuit of claim 14 , wherein the second trigger circuit comprises a GaN based transistor, comprising a first source/drain, a second source/drain and a gate, wherein the first source/drain and the second source/drain of the GaN based transistor are coupled to the first terminal of the second trigger circuit, and the gate of the GaN based transistor is coupled to the second terminal of the second trigger circuit.