Method for packaging semiconductor, semiconductor package structure, and package

1. A method for packaging a semiconductor, comprising:

providing a substrate wafer, the substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, wherein a plurality of electrically conductive pillars are provided at a bottom of a given one of the plurality of grooves, and the plurality of electrically conductive pillars penetrate through the bottom of the given groove to the second surface of the substrate wafer;

providing a plurality of semiconductor die stacks in the plurality of grooves such that a given one of the plurality of semiconductor die stacks is provided in a corresponding one of the plurality of grooves, wherein an upper surface of the given semiconductor die stack is lower than or flush with an upper edge of the corresponding groove, and a bottom of the given semiconductor die stack is electrically connected to the plurality of electrically conductive pillars provided at the bottom of the corresponding groove; and

filling an insulating dielectric in gaps among sidewalls of the plurality of grooves and the plurality of semiconductor die stacks to form an insulating dielectric layer, the insulating dielectric layer covering upper surface of the plurality of semiconductor die stacks to seal up the plurality of semiconductor die stacks to form a semiconductor package structure.

2. The method for packaging a semiconductor according to claim 1 , wherein the second surface of the substrate wafer has a plurality of electrically conductive blocks, wherein a given one of the plurality of electrically conductive blocks is electrically connected to a corresponding electrically conductive pillar.

3. The method for packaging a semiconductor according to claim 1 , wherein the method of forming a groove on the substrate wafer comprises:

planarizing the first surface of the substrate wafer; and

removing a part of the substrate wafer from the first surface until the electrically conductive pillar is exposed to form the groove.

4. The method for packaging a semiconductor according to claim 3 , wherein the substrate wafer has dicing lanes, and the dicing lanes are used for alignment to form the groove.

5. The method for packaging a semiconductor according to claim 1 , wherein each of the plurality of semiconductor die stacks is formed by stacking a plurality of semiconductor dies electrically connected to each other, and the bottom of the given semiconductor die stack is electrically connected to the plurality of electrically conductive pillars provided at the bottom of the corresponding groove through a plurality of electrically conductive blocks provided at the bottom of the given groove.

6. The method for packaging a semiconductor according to claim 5 , wherein the plurality of semiconductor dies are electrically connected to each other through a plurality of electrically conductive pillars penetrating through each of the plurality of semiconductor dies and a plurality of electrically conductive blocks between the adjacent semiconductor dies.

7. The method for packaging a semiconductor according to claim 1 , wherein a thermal expansion coefficient of the substrate wafer is greater than or equal to that of the insulating dielectric layer.

8. The method for packaging a semiconductor according to claim 7 , wherein the substrate wafer is a silicon wafer, and the insulating dielectric layer is a silicon dioxide insulating dielectric layer.

9. The method for packaging a semiconductor according to 1 , further comprising: covering an upper surface of the insulating dielectric layer and the first surface of the substrate wafer with a cover plate wafer.

10. The method for packaging a semiconductor according to claim 9 , wherein a surface of the cover plate wafer facing toward the substrate wafer has a plurality of electrically conductive pillars, and a given one of the plurality of electrically conductive pillars of the cover plate is electrically connected to the upper surface of the corresponding semiconductor die stack through an electrically conductive structure in the insulating dielectric layer.

11. The method for packaging a semiconductor according to claim 1 , wherein after sealing up the semiconductor die stack, the method further comprises dicing the semiconductor package structure along the gap between the grooves to form a plurality of packages independent of each other.

12. A semiconductor package structure, comprising:

a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, wherein a plurality of electrically conductive pillars are provided at a bottom of a given one of the plurality of grooves, and the plurality of electrically conductive pillars penetrate through the bottom of the given groove to the second surface of the substrate wafer;

a plurality of semiconductor die stacks placed in the plurality of grooves such that a given one of the plurality of semiconductor die stacks is provided in a corresponding one of the plurality of grooves, wherein an upper surface of the given semiconductor die stack is lower than or flush with an upper edge of the corresponding groove, and a bottom of the given semiconductor die stack is electrically connected to the plurality of electrically conductive pillars provided at the bottom of the corresponding groove; and

an insulating dielectric layer filling gaps among sidewalls of the plurality of grooves and the plurality of semiconductor die stacks, the insulating dielectric layer being covering the upper surface of the plurality of semiconductor die stacks to seal up the plurality of semiconductor die stacks.

13. The semiconductor package structure according to claim 12 , wherein the second surface of the substrate wafer has a plurality of electrically conductive blocks, wherein a given one of the plurality of electrically conductive blocks is electrically connected to a corresponding electrically conductive pillar.

14. The semiconductor package structure according to claim 12 , wherein each of the plurality of semiconductor die stacks is formed by stacking a plurality of semiconductor dies electrically connected to each other, and the bottom of the given semiconductor die stack is electrically connected to the plurality of electrically conductive pillars provided at the bottom of the corresponding groove through a plurality of electrically conductive blocks provided at the bottom of the given groove.

15. The semiconductor package structure according to claim 14 , wherein the plurality of semiconductor dies are electrically connected to each other through a plurality of electrically conductive pillars penetrating through each of the plurality of semiconductor dies and a plurality of electrically conductive blocks between the adjacent semiconductor dies.

16. The semiconductor package structure according to claim 12 , wherein a thermal expansion coefficient of the substrate wafer is greater than or equal to that of the insulating dielectric layer.

17. The semiconductor package structure according to claim 12 , wherein the substrate wafer is a silicon wafer, and the insulating dielectric layer is a silicon dioxide insulating dielectric layer.

18. The semiconductor package structure according to 12 , wherein an upper surface of the insulating dielectric layer and the first surface of the substrate wafer are covered with a cover plate wafer.

19. The semiconductor package structure according to claim 18 , wherein a surface of the cover plate wafer facing toward the substrate wafer has a plurality of electrically conductive pillars, an electrically conductive structure is provided in the insulating dielectric layer, and a given one of the plurality of electrically conductive pillars of the cover plate is electrically connected to the upper surface of the corresponding semiconductor die stack through the electrically conductive structure.

20. A package, comprising:

a substrate having a first surface and a second surface arranged opposite to each other, the first surface having at least one groove, wherein a plurality of electrically conductive pillars are provided at a bottom of a given one of the plurality of grooves, and the plurality of electrically conductive pillars penetrate through the bottom of the given groove to the second surface of the substrate wafer;

at least one semiconductor die stack placed in the given groove, wherein an upper surface of the given semiconductor die stack is lower than or flush with an upper edge of the corresponding groove, and a bottom of the given semiconductor die stack is electrically connected to the plurality of electrically conductive pillars provided at the bottom of the corresponding groove; and

an insulating dielectric layer filling gaps among sidewalls of the plurality of grooves and the plurality of semiconductor die stacks, the insulating dielectric layer being covering the upper surface of the plurality of semiconductor die stacks to seal up the plurality of semiconductor die stacks.