IP Library Granted Patent US 11,995,417
Granted Patent B2
US 11,995,417 · App. 18/342,385 · Granted May 28, 2024

Neural processing unit, neural processing system, and application system

Inventors: Young Nam Hwang (Hwaseong-si, KR); Hyung-Dal Kwon (Hwaseong-si, KR); Dae Hyun Kim (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F7/5443G06F17/15G06N3/045G06N3/063
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Quick Facts
Patent No.
US 11,995,417
App. No.
18/342,385
Granted
May 28, 2024
Kind
B2
Abstract

Provided is a neural processing unit that performs application-work including a first neural network operation, the neural processing unit includes a first processing core configured to execute the first neural network operation, a hardware block reconfigurable as a hardware core configured to perform hardware block-work, and at least one processor configured to execute computer-readable instructions to distribute a part of the application-work as the hardware block-work to the hardware block based on a first workload of the first processing core.

Claims (39)

1. A neural processing unit comprising:

a hardware block reconfigurable as

a first hardware core configured to execute an operation of a first neural network, or

a second hardware core configured to execute an operation of a second neural network different from the first neural network;

an internal memory storing function data used to execute the operation of the first neural network or the operation of the second neural network; and

at least one processor configured to execute computer-readable instructions to reconfigure the hardware block as the first hardware core or the second hardware core.

2. The neural processing unit of claim 1 , wherein

at least one processor is configured to execute computer-readable instructions to

cause function data used for the operation of the first neural network to be stored in the internal memory when the hardware block is reconfigured as the first hardware core, and

cause function data used for the operation of the second neural network to be stored in the internal memory when the hardware block is reconfigured as the second hardware core.

3. The neural processing unit of claim 1 , wherein

at least one processor is configured to execute computer-readable instructions to cause internal memory to update the function data stored in the internal memory in accordance with an operation being executed on the first hardware core or the second hardware core.

4. The neural processing unit of claim 3 , wherein at least one processor is configured to execute computer-readable instructions to cause the internal memory to update the function data by causing the internal memory to delete the function data stored in the internal memory and to causing the internal memory to store new function data received from a memory outside the neural processing unit.

5. The neural processing unit of claim 1 , wherein the function data comprises sigmoid, tanh (hyperbolic tangent) or ReLU (Rectified Linear Unit) function data.

6. The neural processing unit of claim 1 , further comprising:

a first processing core configured to execute the operation of the first neural network.

7. The neural processing unit of claim 6 , wherein the neural processing unit configured to perform application-work, and

at least one processor is configured to execute computer-readable instructions to distribute a part of the application-work as a hardware block-work to the hardware block based on a first workload of the first processing core.

8. The neural processing unit of claim 6 , further comprising:

a second processing core configured to execute the operation of the second neural network.

9. The neural processing unit of claim 8 , wherein the neural processing unit configured to perform application-work, and

at least one processor is configured to execute computer-readable instructions to distribute a part of the application-work as a hardware block-work to the hardware block based on a first workload of the first processing core and a second workload of the second processing core.

10. A neural processing system comprising:

an external memory storing meta data usable for reconfiguring a hardware block;

a neural processing unit including a first processing core and the hardware block, the first processing core being configured to perform an operation of a first neural network; and

at least one processor configured to execute computer-readable instructions to reconfigure the hardware block as the first processing core or a second processing core being configured to perform an operation of a second neural network different from the operation of the first neural network using the meta data stored in the external memory.

11. The neural processing system of claim 10 , wherein the external memory stores

first reconfiguration data usable for reconfiguring the hardware block as a first hardware core configured to execute the operation of the first neural network, or

second reconfiguration data usable for reconfiguring the hardware block as a second hardware core configured to execute an operation of a second neural network different from the first neural network.

12. The neural processing system of claim 10 , wherein

the operation of the first neural network comprises a MAC operation, and

the external memory stores a third reconfiguration data usable for reconfiguring the hardware block as a MAC processing hardware core, the third reconfiguration data including a look-up table including quantized weight information.

13. The neural processing system of claim 10 , wherein

the external memory stores function data used in the first processing core or the hardware block, and

the neural processing unit includes at least one processor configured to execute computer-readable instructions to obtain the function data from the external memory in accordance with an operation being performed in the first processing core or the hardware block.

14. The neural processing unit of claim 10 , wherein the neural processing unit configured to perform application-work, and

at least one processor is configured to execute computer-readable instructions to distribute a part of the application-work as a hardware block-work to the hardware block based on a first workload of the first processing core.

15. The neural processing unit of claim 10 , further comprising:

an internal memory storing function data used to execute the operation of the first neural network or the operation of the second neural network.

Priority Claims (1)
KR 10-2018-0137345 · Nov 9, 2018 · national
Continuity (2)
Continuation 16439928 · Jun 13, 2019
Related Publication 20230342113A1 · Oct 26, 2023
Cited By (2)
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