Dynamic vision sensor architecture
A dynamic vision sensor (DVS) or change detection sensor reacts to changes in light intensity and in this way monitors how a scene changes. This disclosure covers both single pixel and array architectures. The DVS may contain one pixel or 2-dimensional or 1-dimensional array of pixels. The change of intensities registered by pixels are compared, and pixel addresses where the change is positive or negative are recorded and processed. Analyzing frames based on just three values for pixels, increase, decrease or unchanged, the proposed DVS can process visual information much faster than traditional computer vision systems, which correlate multi-bit color or gray level pixel values between successive frames.
1. An imaging device comprising:
a photoelectric conversion region;
first circuitry coupled to the photoelectric conversion region;
a first capacitor coupled to the first circuitry;
comparison circuitry coupled to the first capacitor that compares a first signal based on an output from the photoelectric conversion region to both a first reference voltage and a second reference voltage selectively and that includes a first terminal that receives the first signal and a second terminal that receives the first reference voltage and the second reference voltage selectively, and
reset circuitry that resets the first capacitor based on an output from the comparison circuitry and a global reset signal.
2. The device as claimed in claim 1 , wherein the output from the comparison circuitry includes ON event signals and OFF event signals.
3. The device as claimed in claim 1 , wherein the comparison circuitry outputs ON event signals during ON comparison phases and OFF event signals during OFF comparison phases.
4. The device as claimed in claim 1 , wherein the first reference voltage is coupled to the second terminal during ON comparison phases.
5. The device as claimed in claim 4 , wherein the second reference voltage is coupled to the second terminal during OFF comparison phases.
6. The device as claimed in claim 5 , wherein the second terminal receives a third reference voltage during reset phases.
7. The device as claimed in claim 6 , further comprising controller circuitry that controls the switching of the first reference voltage, the second reference voltage and third reference voltage.
8. The device as claimed in claim 1 , wherein the reset circuitry includes a logical AND operator.
9. The device as claimed in claim 1 , further comprising memory circuitry that stores the output from the comparison circuitry.
10. The device as claimed in claim 9 , further comprising readout circuitry that controls the memory circuitry to read the output from the comparison circuitry.
11. The device as claimed in claim 1 , wherein the first circuitry includes logarithm circuit.
12. An imaging device comprising an array of pixels, wherein each of the pixels includes:
a photoelectric conversion region;
first circuitry coupled to the photoelectric conversion region;
a first capacitor coupled to the first circuitry;
comparison circuitry coupled to the first capacitor that compares a first signal based on an output from the photoelectric conversion region to both a first reference voltage and a second reference voltage selectively and that includes a first terminal that receives the first signal and a second terminal that receives the first reference voltage and the second reference voltage selectively, and
reset circuitry that resets the first capacitor based on an output from the comparison circuitry and a global reset signal.
13. The device as claimed in claim 12 , wherein the output from the comparison circuitry includes ON event signals and OFF event signals.
14. The device as claimed in claim 12 , wherein the comparison circuitry outputs ON event signals during ON comparison phases and OFF event signals during OFF comparison phases.
15. The device as claimed in claim 12 , wherein the first reference voltage is coupled to the second terminal during ON comparison phases and the second reference voltage is coupled to the second terminal during OFF comparison phases.
16. The device as claimed in claim 15 , wherein the second terminal receives a third reference voltage during reset phases.
17. The device as claimed in claim 16 , further comprising controller circuitry that controls the switching of the first reference voltage, the second reference voltage and third reference voltage.
18. The device as claimed in claim 12 , wherein the reset circuitry includes a logical AND operator.
19. The device as claimed in claim 12 , further comprising memory circuitry that stores the output from the comparison circuitry and readout circuitry that controls the memory circuitry to read the output from the comparison circuitry.
20. The device as claimed in claim 12 , wherein the first circuitry includes logarithm circuit.