System and method for ESL modeling of machine learning

1. A method of designing a semiconductor device using electronic system level (ESL) modeling for machine learning applications, the method comprising:

receiving source code that embodies a plurality of operations of a machine learning algorithm;

classifying a first group of the plurality of operations as slow group operations and classifying a second group of the plurality of operations as fast group operations, based on the time required to complete each operation;

defining a neural network suitable for executing the slow group operations;

mapping the neural network onto a machine learning hardware configuration;

verifying successful execution of a first slow group operation on a final machine learning hardware configuration; and

modeling the final machine learning hardware configuration as a semiconductor device using standard cell designs selected from a predefined model library.

2. The method according to claim 1 , wherein:

defining the neural network further comprises defining

a plurality of nodes and

a plurality of interconnections between nodes of the plurality of nodes; and

assigning an initial interconnection weight to each interconnection of the plurality of interconnections in the machine learning hardware configuration.

3. The method according to claim 2 , further comprising:

assigning each node of the plurality of nodes of the neural network to a corresponding processing element on an application specific integrated circuit (ASIC) semiconductor device.

4. The method according to claim 2 , further comprising:

applying a first training data set to the machine learning hardware configuration to generate first error values; and

backpropagating the first error values through the neural network to adjust each of the interconnection weights and generate a first trained machine learning hardware configuration.

5. The method according to claim 4 , further comprising:

applying the first training data set to the first trained machine learning hardware configuration to generate second error values; and

backpropagating the second error values through the neural network to adjust each of the interconnection weights and generate a second trained machine learning hardware configuration.

6. The method according to claim 4 , further comprising:

applying an x th training data set to an n th trained machine learning hardware configuration to generate (n+1) th error values; and

backpropagating the set of (n+1) th error values through the neural network to adjust each of the interconnection weights and generate a (n+1) th trained machine learning hardware configuration.

7. The method according to claim 6 , wherein:

the first training data set and the x th training data set are different.

8. The method according to claim 1 , wherein the defining the neural network further comprises:

defining an input layer including a plurality of input nodes;

defining a first hidden layer including a first plurality of hidden nodes; and

defining an output layer including at least one output node.

9. The method according to claim 8 , further comprising:

defining a second hidden layer including a second plurality of hidden nodes.

10. The method according to claim 8 , further comprising:

applying a first test data set to a (n+1) th trained machine learning hardware configuration to generate a failing test result or a passing test result;

in response to the failing test result,

modifying the (n+1) th trained machine learning hardware configuration to generate a revised machine learning hardware configuration;

applying a second test data set to the revised machine learning hardware configuration to generate the failing test result or the passing test result;

modifying the revised machine learning hardware configuration and applying the second test data set until the passing test result is obtained with a final machine learning hardware configuration;

in response to the passing test result, outputting a design file corresponding to the final machine learning hardware configuration;

generating a machine learning software code for executing the fast group operations; and

executing the machine learning software code to complete the fast group operations in support of the slow group operations.

11. The method according to claim 10 , wherein:

the first test data set and the second test data set are not identical.

12. The method according to claim 10 , further comprising:

outputting a device design file corresponding to the final machine learning hardware configuration in response to the passing test result;

generating a machine learning software code for executing the fast group operation; and

executing the machine learning software code to complete the fast group operation in support of the slow group operation.

13. The method according to claim 12 , further comprising:

fabricating the final machine learning hardware configuration as an ASIC design comprising a plurality of processing elements wherein each node of the plurality of nodes of a neuron network corresponds to a processing element on the ASIC design.

14. A method of designing a semiconductor device using electronic system level (ESL) modeling for machine learning applications, the method comprising:

retrieving a source code from a non-transitory computer readable storage medium, the source code being operable to execute a plurality of operations of a machine learning algorithm;

classifying a first group of the plurality of operations as slow group operations and classifying a second group of the plurality of operations as fast group operations, based on the time required to complete each operation;

defining a neural network suitable for executing the slow group operations;

defining a trained neural network configuration comprising a plurality of interconnected neurons suitable for executing the slow group operations; and

generating an ESL platform for evaluating a design of a semiconductor device based on the trained neural network configuration.

15. The method of designing a semiconductor device according to claim 14 , the method further comprising:

identifying a plurality of fast group operations;

defining a machine learning code for executing the fast group operations in conjunction with the trained neural network; and

defining a memory subsystem operable to execute the machine learning code.

16. The method of designing a semiconductor device according to claim 15 , the method further comprising:

defining the memory subsystem using a plurality of design elements selected from the group consisting of GPU, CPU, DSP, RAM, ROM, DMA, IP, and interconnectors.

17. The method of designing a semiconductor device according to claim 15 , the method further comprising:

generating an ASIC device design comprising a plurality of processing units corresponding to the trained neural network configuration.

18. A method of designing a semiconductor device using electronic system level (ESL) modeling for machine learning applications, the method comprising:

retrieving a source code from a non-transitory computer readable storage medium, the source code being operable to execute a plurality of operations of a machine learning algorithm;

categorizing each operation of the plurality of operations as a fast group operation or a slow group operation, based on the time required to complete each operation; and

generating a machine learning hardware module configured as a neuron network operable to execute the each of the operations categorized as a slow group operation.

19. The method of designing a semiconductor device according to claim 18 , the method further comprising:

emulating a memory subsystem hardware module; and

emulating a machine learning hardware module.

20. The method of designing a semiconductor device according to claim 19 , the method further comprising:

generating a semiconductor device layout for fabricating a semiconductor device comprising both the memory subsystem hardware module and the machine learning hardware module.